/*
 * Copyright (C) 2019 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See http://www.gnu.org/licenses/gpl-2.0.html for more details.
 */
#ifndef __CONN_INFRA_CFG_REGS_H__
#define __CONN_INFRA_CFG_REGS_H__

#define CONN_INFRA_CFG_BASE                                    0x18001000

#define CONN_INFRA_CFG_CONN_HW_VER_ADDR                        (CONN_INFRA_CFG_BASE + 0x0000)
#define CONN_INFRA_CFG_CONN_CFG_ID_ADDR                        (CONN_INFRA_CFG_BASE + 0x0004)
#define CONN_INFRA_CFG_CONN_FPGA_DUMMY0_ADDR                   (CONN_INFRA_CFG_BASE + 0x0010)
#define CONN_INFRA_CFG_CONN_FPGA_DUMMY1_ADDR                   (CONN_INFRA_CFG_BASE + 0x0014)
#define CONN_INFRA_CFG_EASY_SECURITY_WF_IRQ_CLR_ADDR           (CONN_INFRA_CFG_BASE + 0x00E0)
#define CONN_INFRA_CFG_EASY_SECURITY_BGF_IRQ_CLR_ADDR          (CONN_INFRA_CFG_BASE + 0x00E4)
#define CONN_INFRA_CFG_LIGHT_SECURITY_CTRL_ADDR                (CONN_INFRA_CFG_BASE + 0x00F0)
#define CONN_INFRA_CFG_BUS_DEAD_CR_ADDRESS_ADDR                (CONN_INFRA_CFG_BASE + 0x00FC)
#define CONN_INFRA_CFG_AP2BGF_REMAP_0_ADDR                     (CONN_INFRA_CFG_BASE + 0x0100)
#define CONN_INFRA_CFG_AP2BGF_REMAP_1_ADDR                     (CONN_INFRA_CFG_BASE + 0x0104)
#define CONN_INFRA_CFG_AP2BGF_REMAP_2_ADDR                     (CONN_INFRA_CFG_BASE + 0x0108)
#define CONN_INFRA_CFG_AP2BGF_REMAP_SEG_0_ADDR                 (CONN_INFRA_CFG_BASE + 0x010C)
#define CONN_INFRA_CFG_AP2BGF_REMAP_SEG_1_ADDR                 (CONN_INFRA_CFG_BASE + 0x0110)
#define CONN_INFRA_CFG_SUBSYS2AP_REMAP_0_ADDR                  (CONN_INFRA_CFG_BASE + 0x0114)
#define CONN_INFRA_CFG_AP2BGF_REMAP_3_ADDR                     (CONN_INFRA_CFG_BASE + 0x0118)
#define CONN_INFRA_CFG_AP2WF_REMAP_0_ADDR                      (CONN_INFRA_CFG_BASE + 0x011C)
#define CONN_INFRA_CFG_AP2WF_REMAP_1_ADDR                      (CONN_INFRA_CFG_BASE + 0x0120)
#define CONN_INFRA_CFG_AP2WF_REMAP_2_ADDR                      (CONN_INFRA_CFG_BASE + 0x0124)
#define CONN_INFRA_CFG_AP2WF_REMAP_SEG_0_ADDR                  (CONN_INFRA_CFG_BASE + 0x0128)
#define CONN_INFRA_CFG_AP2WF_REMAP_SEG_1_ADDR                  (CONN_INFRA_CFG_BASE + 0x012C)
#define CONN_INFRA_CFG_AP2WF_REMAP_3_ADDR                      (CONN_INFRA_CFG_BASE + 0x0134)
#define CONN_INFRA_CFG_GALS_CONN2BT_GALS_DBG_ADDR              (CONN_INFRA_CFG_BASE + 0x0150)
#define CONN_INFRA_CFG_GALS_CONN2GPS_GALS_DBG_ADDR             (CONN_INFRA_CFG_BASE + 0x0154)
#define CONN_INFRA_CFG_GALS_AP2CONN_GALS_DBG_ADDR              (CONN_INFRA_CFG_BASE + 0x0160)
#define CONN_INFRA_CFG_GALS_AP2CONN_CTRL_1_ADDR                (CONN_INFRA_CFG_BASE + 0x0164)
#define CONN_INFRA_CFG_GALS_CONN2AP_GALS_DBG_ADDR              (CONN_INFRA_CFG_BASE + 0x0168)
#define CONN_INFRA_CFG_GALS_CONN2AP_CTRL_1_ADDR                (CONN_INFRA_CFG_BASE + 0x016C)
#define CONN_INFRA_CFG_GALS_BT2CONN_GALS_DBG_ADDR              (CONN_INFRA_CFG_BASE + 0x0170)
#define CONN_INFRA_CFG_GALS_BT2CONN_CTRL_1_ADDR                (CONN_INFRA_CFG_BASE + 0x0174)
#define CONN_INFRA_CFG_GALS_GPS2CONN_GALS_DBG_ADDR             (CONN_INFRA_CFG_BASE + 0x0178)
#define CONN_INFRA_CFG_GALS_GPS2CONN_CTRL_1_ADDR               (CONN_INFRA_CFG_BASE + 0x017C)
#define CONN_INFRA_CFG_GALS_CONN2BT_CTRL_1_ADDR                (CONN_INFRA_CFG_BASE + 0x0180)
#define CONN_INFRA_CFG_GALS_CONN2GPS_CTRL_1_ADDR               (CONN_INFRA_CFG_BASE + 0x0184)
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_ADDR                (CONN_INFRA_CFG_BASE + 0x0188)
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_1_ADDR                (CONN_INFRA_CFG_BASE + 0x018C)
#define CONN_INFRA_CFG_PCIE2AP_REMAP_0_ADDR                    (CONN_INFRA_CFG_BASE + 0x0190)
#define CONN_INFRA_CFG_PCIE2AP_REMAP_1_ADDR                    (CONN_INFRA_CFG_BASE + 0x0194)
#define CONN_INFRA_CFG_PCIE2AP_REMAP_2_ADDR                    (CONN_INFRA_CFG_BASE + 0x0198)
#define CONN_INFRA_CFG_PCIE2AP_REMAP_3_ADDR                    (CONN_INFRA_CFG_BASE + 0x019C)
#define CONN_INFRA_CFG_PCIE2AP_REMAP_4_ADDR                    (CONN_INFRA_CFG_BASE + 0x01A0)
#define CONN_INFRA_CFG_PCIE2AP_REMAP_5_ADDR                    (CONN_INFRA_CFG_BASE + 0x01A4)
#define CONN_INFRA_CFG_PCIE2AP_REMAP_6_ADDR                    (CONN_INFRA_CFG_BASE + 0x01A8)
#define CONN_INFRA_CFG_PCIE2AP_REMAP_7_ADDR                    (CONN_INFRA_CFG_BASE + 0x01AC)
#define CONN_INFRA_CFG_LEGACY_REMAP_CTRL_0_ADDR                (CONN_INFRA_CFG_BASE + 0x01B0)
#define CONN_INFRA_CFG_LEGACY_REMAP_CTRL_1_ADDR                (CONN_INFRA_CFG_BASE + 0x01B4)
#define CONN_INFRA_CFG_LEGACY_REMAP_CTRL_2_ADDR                (CONN_INFRA_CFG_BASE + 0x01B8)
#define CONN_INFRA_CFG_LEGACY_REMAP_CTRL_3_ADDR                (CONN_INFRA_CFG_BASE + 0x01BC)
#define CONN_INFRA_CFG_LEGACY_REMAP_CTRL_4_ADDR                (CONN_INFRA_CFG_BASE + 0x01C0)
#define CONN_INFRA_CFG_LEGACY_REMAP_CTRL_5_ADDR                (CONN_INFRA_CFG_BASE + 0x01C4)
#define CONN_INFRA_CFG_LEGACY_REMAP_CTRL_6_ADDR                (CONN_INFRA_CFG_BASE + 0x01C8)
#define CONN_INFRA_CFG_WF_LIGHT_SECURITY_START_ADDR_0_ADDR     (CONN_INFRA_CFG_BASE + 0x0200)
#define CONN_INFRA_CFG_WF_LIGHT_SECURITY_END_ADDR_0_ADDR       (CONN_INFRA_CFG_BASE + 0x0204)
#define CONN_INFRA_CFG_WF_LIGHT_SECURITY_START_ADDR_1_ADDR     (CONN_INFRA_CFG_BASE + 0x0208)
#define CONN_INFRA_CFG_WF_LIGHT_SECURITY_END_ADDR_1_ADDR       (CONN_INFRA_CFG_BASE + 0x020C)
#define CONN_INFRA_CFG_WF_LIGHT_SECURITY_START_ADDR_2_ADDR     (CONN_INFRA_CFG_BASE + 0x0210)
#define CONN_INFRA_CFG_WF_LIGHT_SECURITY_END_ADDR_2_ADDR       (CONN_INFRA_CFG_BASE + 0x0214)
#define CONN_INFRA_CFG_BT_LIGHT_SECURITY_START_ADDR_0_ADDR     (CONN_INFRA_CFG_BASE + 0x0218)
#define CONN_INFRA_CFG_BT_LIGHT_SECURITY_END_ADDR_0_ADDR       (CONN_INFRA_CFG_BASE + 0x021C)
#define CONN_INFRA_CFG_BT_LIGHT_SECURITY_START_ADDR_1_ADDR     (CONN_INFRA_CFG_BASE + 0x0220)
#define CONN_INFRA_CFG_BT_LIGHT_SECURITY_END_ADDR_1_ADDR       (CONN_INFRA_CFG_BASE + 0x0224)
#define CONN_INFRA_CFG_BT_LIGHT_SECURITY_START_ADDR_2_ADDR     (CONN_INFRA_CFG_BASE + 0x0228)
#define CONN_INFRA_CFG_BT_LIGHT_SECURITY_END_ADDR_2_ADDR       (CONN_INFRA_CFG_BASE + 0x022C)
#define CONN_INFRA_CFG_BGF_DUMMY_CR_0_ADDR                     (CONN_INFRA_CFG_BASE + 0x0270)
#define CONN_INFRA_CFG_BGF_DUMMY_CR_1_ADDR                     (CONN_INFRA_CFG_BASE + 0x0274)
#define CONN_INFRA_CFG_BGF_DUMMY_CR_2_ADDR                     (CONN_INFRA_CFG_BASE + 0x0278)
#define CONN_INFRA_CFG_BGF_DUMMY_CR_3_ADDR                     (CONN_INFRA_CFG_BASE + 0x027C)
#define CONN_INFRA_CFG_WF_DUMMY_CR_0_ADDR                      (CONN_INFRA_CFG_BASE + 0x0280)
#define CONN_INFRA_CFG_WF_DUMMY_CR_1_ADDR                      (CONN_INFRA_CFG_BASE + 0x0284)
#define CONN_INFRA_CFG_WF_DUMMY_CR_2_ADDR                      (CONN_INFRA_CFG_BASE + 0x0288)
#define CONN_INFRA_CFG_WF_DUMMY_CR_3_ADDR                      (CONN_INFRA_CFG_BASE + 0x028C)
#define CONN_INFRA_CFG_HOST_CSR_IRQ_EN_ADDR                    (CONN_INFRA_CFG_BASE + 0x0400)
#define CONN_INFRA_CFG_CSR_WF_B0_ON_IRQ_STATUS_ADDR            (CONN_INFRA_CFG_BASE + 0x0404)
#define CONN_INFRA_CFG_CSR_WF_B0_ON_HOST_CSR_MISC_ADDR         (CONN_INFRA_CFG_BASE + 0x0408)
#define CONN_INFRA_CFG_CSR_WF_B1_ON_IRQ_STATUS_ADDR            (CONN_INFRA_CFG_BASE + 0x040C)
#define CONN_INFRA_CFG_CSR_WF_B1_ON_HOST_CSR_MISC_ADDR         (CONN_INFRA_CFG_BASE + 0x0410)
#define CONN_INFRA_CFG_CSR_MD_ON_IRQ_STATUS_ADDR               (CONN_INFRA_CFG_BASE + 0x0414)
#define CONN_INFRA_CFG_CSR_MD_ON_HOST_CSR_MISC_ADDR            (CONN_INFRA_CFG_BASE + 0x0418)
#define CONN_INFRA_CFG_CSR_BGF_ON_IRQ_STATUS_ADDR              (CONN_INFRA_CFG_BASE + 0x041C)
#define CONN_INFRA_CFG_CSR_BGF_ON_HOST_CSR_MISC_ADDR           (CONN_INFRA_CFG_BASE + 0x0420)
#define CONN_INFRA_CFG_CSR_GPS_ON_IRQ_STATUS_ADDR              (CONN_INFRA_CFG_BASE + 0x0424)
#define CONN_INFRA_CFG_CSR_GPS_ON_HOST_CSR_MISC_ADDR           (CONN_INFRA_CFG_BASE + 0x0428)
#define CONN_INFRA_CFG_CSR_BGF_ON_FW_OWN_IRQ_ADDR              (CONN_INFRA_CFG_BASE + 0x042C)
#define CONN_INFRA_CFG_CSR_INFRA_BUS_IDLE_DEBOUNCE_CR_ADDR     (CONN_INFRA_CFG_BASE + 0x04F0)
#define CONN_INFRA_CFG_CSR_INFRA_BUS_IDLE_EN_ADDR              (CONN_INFRA_CFG_BASE + 0x04F4)
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_0_ADDR           (CONN_INFRA_CFG_BASE + 0x0500)
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_1_ADDR           (CONN_INFRA_CFG_BASE + 0x0504)
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_2_ADDR           (CONN_INFRA_CFG_BASE + 0x0508)
#define CONN_INFRA_CFG_GALS_WFDMA_SLP_EN_ADDR                  (CONN_INFRA_CFG_BASE + 0x060C)
#define CONN_INFRA_CFG_GALS_CONN2BT_SLP_CTRL_ADDR              (CONN_INFRA_CFG_BASE + 0x0610)
#define CONN_INFRA_CFG_GALS_BT2CONN_SLP_CTRL_ADDR              (CONN_INFRA_CFG_BASE + 0x0614)
#define CONN_INFRA_CFG_GALS_CONN2GPS_SLP_CTRL_ADDR             (CONN_INFRA_CFG_BASE + 0x0618)
#define CONN_INFRA_CFG_GALS_GPS2CONN_SLP_CTRL_ADDR             (CONN_INFRA_CFG_BASE + 0x061C)
#define CONN_INFRA_CFG_CONN_INFRA_WF_SLP_CTRL_ADDR             (CONN_INFRA_CFG_BASE + 0x0620)
#define CONN_INFRA_CFG_CONN_INFRA_WFDMA_SLP_CTRL_ADDR          (CONN_INFRA_CFG_BASE + 0x0624)
#define CONN_INFRA_CFG_CONN_INFRA_ON_BUS_SLP_CTRL_ADDR         (CONN_INFRA_CFG_BASE + 0x0628)
#define CONN_INFRA_CFG_CONN_INFRA_OFF_BUS_SLP_CTRL_ADDR        (CONN_INFRA_CFG_BASE + 0x062C)
#define CONN_INFRA_CFG_CONN_INFRA_GALS_CONN2AP_TX_SLP_CTRL_ADDR (CONN_INFRA_CFG_BASE + 0x0630)
#define CONN_INFRA_CFG_CONN_INFRA_GALS_CONN2AP_RX_SLP_CTRL_ADDR (CONN_INFRA_CFG_BASE + 0x0634)
#define CONN_INFRA_CFG_CONN_INFRA_GALS_CONN2AP_SLP_CTRL_RST_ADDR (CONN_INFRA_CFG_BASE + 0x0638)
#define CONN_INFRA_CFG_OSC_CTL_0_ADDR                          (CONN_INFRA_CFG_BASE + 0x0800)
#define CONN_INFRA_CFG_OSC_CTL_1_ADDR                          (CONN_INFRA_CFG_BASE + 0x0804)
#define CONN_INFRA_CFG_OSC_MASK_ADDR                           (CONN_INFRA_CFG_BASE + 0x0808)
#define CONN_INFRA_CFG_OSC_STATUS_ADDR                         (CONN_INFRA_CFG_BASE + 0x080C)
#define CONN_INFRA_CFG_PLL_STATUS_ADDR                         (CONN_INFRA_CFG_BASE + 0x0810)
#define CONN_INFRA_CFG_STRAP_STATUS_ADDR                       (CONN_INFRA_CFG_BASE + 0x0814)
#define CONN_INFRA_CFG_EFUSE_ADDR                              (CONN_INFRA_CFG_BASE + 0x0818)
#define CONN_INFRA_CFG_BOOT_ADDR                               (CONN_INFRA_CFG_BASE + 0x0820)
#define CONN_INFRA_CFG_RC_STATUS_ADDR                          (CONN_INFRA_CFG_BASE + 0x0830)
#define CONN_INFRA_CFG_RC_CTL_0_ADDR                           (CONN_INFRA_CFG_BASE + 0x0834)
#define CONN_INFRA_CFG_RC_CTL_0_GPS_ADDR                       (CONN_INFRA_CFG_BASE + 0x0838)
#define CONN_INFRA_CFG_RC_CTL_1_GPS_ADDR                       (CONN_INFRA_CFG_BASE + 0x083C)
#define CONN_INFRA_CFG_RC_CTL_0_BT_ADDR                        (CONN_INFRA_CFG_BASE + 0x0840)
#define CONN_INFRA_CFG_RC_CTL_1_BT_ADDR                        (CONN_INFRA_CFG_BASE + 0x0844)
#define CONN_INFRA_CFG_RC_CTL_0_WF_ADDR                        (CONN_INFRA_CFG_BASE + 0x0848)
#define CONN_INFRA_CFG_RC_CTL_1_WF_ADDR                        (CONN_INFRA_CFG_BASE + 0x084C)
#define CONN_INFRA_CFG_RC_CTL_0_TOP_ADDR                       (CONN_INFRA_CFG_BASE + 0x0850)
#define CONN_INFRA_CFG_RC_CTL_1_TOP_ADDR                       (CONN_INFRA_CFG_BASE + 0x0854)
#define CONN_INFRA_CFG_CONN2AP_MAILBOX_ADDR                    (CONN_INFRA_CFG_BASE + 0x0858)
#define CONN_INFRA_CFG_AP2CONN_MAILBOX_ADDR                    (CONN_INFRA_CFG_BASE + 0x085C)
#define CONN_INFRA_CFG_PWRCTRL0_ADDR                           (CONN_INFRA_CFG_BASE + 0x0860)
#define CONN_INFRA_CFG_FM_PWRCTRL0_ADDR                        (CONN_INFRA_CFG_BASE + 0x0870)
#define CONN_INFRA_CFG_BT_PWRCTRL0_ADDR                        (CONN_INFRA_CFG_BASE + 0x0874)
#define CONN_INFRA_CFG_GPS_PWRCTRL0_ADDR                       (CONN_INFRA_CFG_BASE + 0x0878)
#define CONN_INFRA_CFG_BT_MANUAL_CTRL_ADDR                     (CONN_INFRA_CFG_BASE + 0x0880)
#define CONN_INFRA_CFG_GPS_MANUAL_CTRL_ADDR                    (CONN_INFRA_CFG_BASE + 0x0884)
#define CONN_INFRA_CFG_ADIE_CTL_ADDR                           (CONN_INFRA_CFG_BASE + 0x0900)
#define CONN_INFRA_CFG_CKGEN_BUS_ADDR                          (CONN_INFRA_CFG_BASE + 0x0A00)
#define CONN_INFRA_CFG_DBG_MUX_SEL_ADDR                        (CONN_INFRA_CFG_BASE + 0x0B00)
#define CONN_INFRA_CFG_EMI_CTL_0_ADDR                          (CONN_INFRA_CFG_BASE + 0x0C00)
#define CONN_INFRA_CFG_EMI_CTL_1_ADDR                          (CONN_INFRA_CFG_BASE + 0x0C04)
#define CONN_INFRA_CFG_EMI_PROBE_ADDR                          (CONN_INFRA_CFG_BASE + 0x0C08)
#define CONN_INFRA_CFG_EMI_PROBE_1_ADDR                        (CONN_INFRA_CFG_BASE + 0x0C0C)
#define CONN_INFRA_CFG_EMI_CTL_TOP_ADDR                        (CONN_INFRA_CFG_BASE + 0x0C10)
#define CONN_INFRA_CFG_EMI_CTL_WF_ADDR                         (CONN_INFRA_CFG_BASE + 0x0C14)
#define CONN_INFRA_CFG_EMI_CTL_BT_ADDR                         (CONN_INFRA_CFG_BASE + 0x0C18)
#define CONN_INFRA_CFG_EMI_CTL_GPS_ADDR                        (CONN_INFRA_CFG_BASE + 0x0C1C)


#define CONN_INFRA_CFG_CONN_HW_VER_RO_CONN_HW_VERSION_ADDR     CONN_INFRA_CFG_CONN_HW_VER_ADDR
#define CONN_INFRA_CFG_CONN_HW_VER_RO_CONN_HW_VERSION_MASK     0xFFFFFFFF
#define CONN_INFRA_CFG_CONN_HW_VER_RO_CONN_HW_VERSION_SHFT     0

#define CONN_INFRA_CFG_CONN_CFG_ID_RO_CONN_CFG_ID_ADDR         CONN_INFRA_CFG_CONN_CFG_ID_ADDR
#define CONN_INFRA_CFG_CONN_CFG_ID_RO_CONN_CFG_ID_MASK         0xFFFFFFFF
#define CONN_INFRA_CFG_CONN_CFG_ID_RO_CONN_CFG_ID_SHFT         0

#define CONN_INFRA_CFG_CONN_FPGA_DUMMY0_R_CONN_FPGA_DUMMY0_ADDR CONN_INFRA_CFG_CONN_FPGA_DUMMY0_ADDR
#define CONN_INFRA_CFG_CONN_FPGA_DUMMY0_R_CONN_FPGA_DUMMY0_MASK 0xFFFFFFFF
#define CONN_INFRA_CFG_CONN_FPGA_DUMMY0_R_CONN_FPGA_DUMMY0_SHFT 0

#define CONN_INFRA_CFG_CONN_FPGA_DUMMY1_R_CONN_FPGA_DUMMY1_ADDR CONN_INFRA_CFG_CONN_FPGA_DUMMY1_ADDR
#define CONN_INFRA_CFG_CONN_FPGA_DUMMY1_R_CONN_FPGA_DUMMY1_MASK 0xFFFFFFFF
#define CONN_INFRA_CFG_CONN_FPGA_DUMMY1_R_CONN_FPGA_DUMMY1_SHFT 0

#define CONN_INFRA_CFG_EASY_SECURITY_WF_IRQ_CLR_R_CONN_INFRA_WF_SECURITY_IRQ_CLR_ADDR \
	CONN_INFRA_CFG_EASY_SECURITY_WF_IRQ_CLR_ADDR
#define CONN_INFRA_CFG_EASY_SECURITY_WF_IRQ_CLR_R_CONN_INFRA_WF_SECURITY_IRQ_CLR_MASK 0x00000001
#define CONN_INFRA_CFG_EASY_SECURITY_WF_IRQ_CLR_R_CONN_INFRA_WF_SECURITY_IRQ_CLR_SHFT 0
#define CONN_INFRA_CFG_EASY_SECURITY_WF_IRQ_CLR_RO_CONN_INFRA_WF_SECURITY_IRQ_STATE_ADDR \
	CONN_INFRA_CFG_EASY_SECURITY_WF_IRQ_CLR_ADDR
#define CONN_INFRA_CFG_EASY_SECURITY_WF_IRQ_CLR_RO_CONN_INFRA_WF_SECURITY_IRQ_STATE_MASK 0x00000002
#define CONN_INFRA_CFG_EASY_SECURITY_WF_IRQ_CLR_RO_CONN_INFRA_WF_SECURITY_IRQ_STATE_SHFT 1

#define CONN_INFRA_CFG_EASY_SECURITY_BGF_IRQ_CLR_R_CONN_INFRA_BGF_SECURITY_IRQ_CLR_ADDR \
	CONN_INFRA_CFG_EASY_SECURITY_BGF_IRQ_CLR_ADDR
#define CONN_INFRA_CFG_EASY_SECURITY_BGF_IRQ_CLR_R_CONN_INFRA_BGF_SECURITY_IRQ_CLR_MASK 0x00000001
#define CONN_INFRA_CFG_EASY_SECURITY_BGF_IRQ_CLR_R_CONN_INFRA_BGF_SECURITY_IRQ_CLR_SHFT 0
#define CONN_INFRA_CFG_EASY_SECURITY_BGF_IRQ_CLR_RO_CONN_INFRA_BGF_SECURITY_IRQ_STATE_ADDR \
	CONN_INFRA_CFG_EASY_SECURITY_BGF_IRQ_CLR_ADDR
#define CONN_INFRA_CFG_EASY_SECURITY_BGF_IRQ_CLR_RO_CONN_INFRA_BGF_SECURITY_IRQ_STATE_MASK 0x00000002
#define CONN_INFRA_CFG_EASY_SECURITY_BGF_IRQ_CLR_RO_CONN_INFRA_BGF_SECURITY_IRQ_STATE_SHFT 1

#define CONN_INFRA_CFG_LIGHT_SECURITY_CTRL_R_CONN_INFRA_WF_PAIR0_EN_ADDR CONN_INFRA_CFG_LIGHT_SECURITY_CTRL_ADDR
#define CONN_INFRA_CFG_LIGHT_SECURITY_CTRL_R_CONN_INFRA_WF_PAIR0_EN_MASK 0x00000001
#define CONN_INFRA_CFG_LIGHT_SECURITY_CTRL_R_CONN_INFRA_WF_PAIR0_EN_SHFT 0
#define CONN_INFRA_CFG_LIGHT_SECURITY_CTRL_R_CONN_INFRA_WF_PAIR1_EN_ADDR CONN_INFRA_CFG_LIGHT_SECURITY_CTRL_ADDR
#define CONN_INFRA_CFG_LIGHT_SECURITY_CTRL_R_CONN_INFRA_WF_PAIR1_EN_MASK 0x00000002
#define CONN_INFRA_CFG_LIGHT_SECURITY_CTRL_R_CONN_INFRA_WF_PAIR1_EN_SHFT 1
#define CONN_INFRA_CFG_LIGHT_SECURITY_CTRL_R_CONN_INFRA_WF_PAIR2_EN_ADDR CONN_INFRA_CFG_LIGHT_SECURITY_CTRL_ADDR
#define CONN_INFRA_CFG_LIGHT_SECURITY_CTRL_R_CONN_INFRA_WF_PAIR2_EN_MASK 0x00000004
#define CONN_INFRA_CFG_LIGHT_SECURITY_CTRL_R_CONN_INFRA_WF_PAIR2_EN_SHFT 2
#define CONN_INFRA_CFG_LIGHT_SECURITY_CTRL_R_CONN_INFRA_BT_PAIR0_EN_ADDR CONN_INFRA_CFG_LIGHT_SECURITY_CTRL_ADDR
#define CONN_INFRA_CFG_LIGHT_SECURITY_CTRL_R_CONN_INFRA_BT_PAIR0_EN_MASK 0x00000008
#define CONN_INFRA_CFG_LIGHT_SECURITY_CTRL_R_CONN_INFRA_BT_PAIR0_EN_SHFT 3
#define CONN_INFRA_CFG_LIGHT_SECURITY_CTRL_R_CONN_INFRA_BT_PAIR1_EN_ADDR CONN_INFRA_CFG_LIGHT_SECURITY_CTRL_ADDR
#define CONN_INFRA_CFG_LIGHT_SECURITY_CTRL_R_CONN_INFRA_BT_PAIR1_EN_MASK 0x00000010
#define CONN_INFRA_CFG_LIGHT_SECURITY_CTRL_R_CONN_INFRA_BT_PAIR1_EN_SHFT 4
#define CONN_INFRA_CFG_LIGHT_SECURITY_CTRL_R_CONN_INFRA_BT_PAIR2_EN_ADDR CONN_INFRA_CFG_LIGHT_SECURITY_CTRL_ADDR
#define CONN_INFRA_CFG_LIGHT_SECURITY_CTRL_R_CONN_INFRA_BT_PAIR2_EN_MASK 0x00000020
#define CONN_INFRA_CFG_LIGHT_SECURITY_CTRL_R_CONN_INFRA_BT_PAIR2_EN_SHFT 5

#define CONN_INFRA_CFG_BUS_DEAD_CR_ADDRESS_CONN_INFRA_DEAD_CR_ADDRESS_ADDR CONN_INFRA_CFG_BUS_DEAD_CR_ADDRESS_ADDR
#define CONN_INFRA_CFG_BUS_DEAD_CR_ADDRESS_CONN_INFRA_DEAD_CR_ADDRESS_MASK 0xFFFFFFFF
#define CONN_INFRA_CFG_BUS_DEAD_CR_ADDRESS_CONN_INFRA_DEAD_CR_ADDRESS_SHFT 0

#define CONN_INFRA_CFG_AP2BGF_REMAP_0_R_AP2BGF_PRIVAT_REMAPPING_0_START_ADDRESS_ADDR CONN_INFRA_CFG_AP2BGF_REMAP_0_ADDR
#define CONN_INFRA_CFG_AP2BGF_REMAP_0_R_AP2BGF_PRIVAT_REMAPPING_0_START_ADDRESS_MASK 0xFFFFFFFF
#define CONN_INFRA_CFG_AP2BGF_REMAP_0_R_AP2BGF_PRIVAT_REMAPPING_0_START_ADDRESS_SHFT 0

#define CONN_INFRA_CFG_AP2BGF_REMAP_1_R_AP2BGF_PUBLIC_REMAPPING_0_START_ADDRESS_ADDR CONN_INFRA_CFG_AP2BGF_REMAP_1_ADDR
#define CONN_INFRA_CFG_AP2BGF_REMAP_1_R_AP2BGF_PUBLIC_REMAPPING_0_START_ADDRESS_MASK 0xFFFFFFFF
#define CONN_INFRA_CFG_AP2BGF_REMAP_1_R_AP2BGF_PUBLIC_REMAPPING_0_START_ADDRESS_SHFT 0

#define CONN_INFRA_CFG_AP2BGF_REMAP_2_R_AP2BGF_PUBLIC_REMAPPING_1_START_ADDRESS_ADDR CONN_INFRA_CFG_AP2BGF_REMAP_2_ADDR
#define CONN_INFRA_CFG_AP2BGF_REMAP_2_R_AP2BGF_PUBLIC_REMAPPING_1_START_ADDRESS_MASK 0xFFFFFFFF
#define CONN_INFRA_CFG_AP2BGF_REMAP_2_R_AP2BGF_PUBLIC_REMAPPING_1_START_ADDRESS_SHFT 0

#define CONN_INFRA_CFG_AP2BGF_REMAP_SEG_0_R_AP2BGF_REMAPPING_SEGMENT_0_ADDR CONN_INFRA_CFG_AP2BGF_REMAP_SEG_0_ADDR
#define CONN_INFRA_CFG_AP2BGF_REMAP_SEG_0_R_AP2BGF_REMAPPING_SEGMENT_0_MASK 0xFFFFFFFF
#define CONN_INFRA_CFG_AP2BGF_REMAP_SEG_0_R_AP2BGF_REMAPPING_SEGMENT_0_SHFT 0

#define CONN_INFRA_CFG_AP2BGF_REMAP_SEG_1_R_AP2BGF_REMAPPING_SEGMENT_1_ADDR CONN_INFRA_CFG_AP2BGF_REMAP_SEG_1_ADDR
#define CONN_INFRA_CFG_AP2BGF_REMAP_SEG_1_R_AP2BGF_REMAPPING_SEGMENT_1_MASK 0xFFFFFFFF
#define CONN_INFRA_CFG_AP2BGF_REMAP_SEG_1_R_AP2BGF_REMAPPING_SEGMENT_1_SHFT 0

#define CONN_INFRA_CFG_SUBSYS2AP_REMAP_0_R_CONN_INFRA_START_ADDRESS_IN_WF_ADDR CONN_INFRA_CFG_SUBSYS2AP_REMAP_0_ADDR
#define CONN_INFRA_CFG_SUBSYS2AP_REMAP_0_R_CONN_INFRA_START_ADDRESS_IN_WF_MASK 0x00FF0000
#define CONN_INFRA_CFG_SUBSYS2AP_REMAP_0_R_CONN_INFRA_START_ADDRESS_IN_WF_SHFT 16
#define CONN_INFRA_CFG_SUBSYS2AP_REMAP_0_R_CONN_INFRA_START_ADDRESS_IN_BGF_ADDR CONN_INFRA_CFG_SUBSYS2AP_REMAP_0_ADDR
#define CONN_INFRA_CFG_SUBSYS2AP_REMAP_0_R_CONN_INFRA_START_ADDRESS_IN_BGF_MASK 0x0000FF00
#define CONN_INFRA_CFG_SUBSYS2AP_REMAP_0_R_CONN_INFRA_START_ADDRESS_IN_BGF_SHFT 8
#define CONN_INFRA_CFG_SUBSYS2AP_REMAP_0_R_CONN_INFRA_START_ADDRESS_IN_AP_ADDR CONN_INFRA_CFG_SUBSYS2AP_REMAP_0_ADDR
#define CONN_INFRA_CFG_SUBSYS2AP_REMAP_0_R_CONN_INFRA_START_ADDRESS_IN_AP_MASK 0x000000FF
#define CONN_INFRA_CFG_SUBSYS2AP_REMAP_0_R_CONN_INFRA_START_ADDRESS_IN_AP_SHFT 0

#define CONN_INFRA_CFG_AP2BGF_REMAP_3_R_AP2BGF_BGF_START_ADDRESS_ADDR CONN_INFRA_CFG_AP2BGF_REMAP_3_ADDR
#define CONN_INFRA_CFG_AP2BGF_REMAP_3_R_AP2BGF_BGF_START_ADDRESS_MASK 0xFFFFFFFF
#define CONN_INFRA_CFG_AP2BGF_REMAP_3_R_AP2BGF_BGF_START_ADDRESS_SHFT 0

#define CONN_INFRA_CFG_AP2WF_REMAP_0_R_AP2WF_PRIVAT_REMAPPING_0_START_ADDRESS_ADDR CONN_INFRA_CFG_AP2WF_REMAP_0_ADDR
#define CONN_INFRA_CFG_AP2WF_REMAP_0_R_AP2WF_PRIVAT_REMAPPING_0_START_ADDRESS_MASK 0xFFFFFFFF
#define CONN_INFRA_CFG_AP2WF_REMAP_0_R_AP2WF_PRIVAT_REMAPPING_0_START_ADDRESS_SHFT 0

#define CONN_INFRA_CFG_AP2WF_REMAP_1_R_AP2WF_PUBLIC_REMAPPING_0_START_ADDRESS_ADDR CONN_INFRA_CFG_AP2WF_REMAP_1_ADDR
#define CONN_INFRA_CFG_AP2WF_REMAP_1_R_AP2WF_PUBLIC_REMAPPING_0_START_ADDRESS_MASK 0xFFFFFFFF
#define CONN_INFRA_CFG_AP2WF_REMAP_1_R_AP2WF_PUBLIC_REMAPPING_0_START_ADDRESS_SHFT 0

#define CONN_INFRA_CFG_AP2WF_REMAP_2_R_AP2WF_PUBLIC_REMAPPING_1_START_ADDRESS_ADDR CONN_INFRA_CFG_AP2WF_REMAP_2_ADDR
#define CONN_INFRA_CFG_AP2WF_REMAP_2_R_AP2WF_PUBLIC_REMAPPING_1_START_ADDRESS_MASK 0xFFFFFFFF
#define CONN_INFRA_CFG_AP2WF_REMAP_2_R_AP2WF_PUBLIC_REMAPPING_1_START_ADDRESS_SHFT 0

#define CONN_INFRA_CFG_AP2WF_REMAP_SEG_0_R_AP2WF_REMAPPING_SEGMENT_0_ADDR CONN_INFRA_CFG_AP2WF_REMAP_SEG_0_ADDR
#define CONN_INFRA_CFG_AP2WF_REMAP_SEG_0_R_AP2WF_REMAPPING_SEGMENT_0_MASK 0xFFFFFFFF
#define CONN_INFRA_CFG_AP2WF_REMAP_SEG_0_R_AP2WF_REMAPPING_SEGMENT_0_SHFT 0

#define CONN_INFRA_CFG_AP2WF_REMAP_SEG_1_R_AP2WF_REMAPPING_SEGMENT_1_ADDR CONN_INFRA_CFG_AP2WF_REMAP_SEG_1_ADDR
#define CONN_INFRA_CFG_AP2WF_REMAP_SEG_1_R_AP2WF_REMAPPING_SEGMENT_1_MASK 0xFFFFFFFF
#define CONN_INFRA_CFG_AP2WF_REMAP_SEG_1_R_AP2WF_REMAPPING_SEGMENT_1_SHFT 0

#define CONN_INFRA_CFG_AP2WF_REMAP_3_R_AP2WF_WF_START_ADDRESS_ADDR CONN_INFRA_CFG_AP2WF_REMAP_3_ADDR
#define CONN_INFRA_CFG_AP2WF_REMAP_3_R_AP2WF_WF_START_ADDRESS_MASK 0xFFFFFFFF
#define CONN_INFRA_CFG_AP2WF_REMAP_3_R_AP2WF_WF_START_ADDRESS_SHFT 0

#define CONN_INFRA_CFG_GALS_CONN2BT_GALS_DBG_RO_CONN2BT_CBIP_GALS_SIDEBAND_GALS_AHB_DBG_SLV_ADDR \
	CONN_INFRA_CFG_GALS_CONN2BT_GALS_DBG_ADDR
#define CONN_INFRA_CFG_GALS_CONN2BT_GALS_DBG_RO_CONN2BT_CBIP_GALS_SIDEBAND_GALS_AHB_DBG_SLV_MASK 0xFFFFFFFF
#define CONN_INFRA_CFG_GALS_CONN2BT_GALS_DBG_RO_CONN2BT_CBIP_GALS_SIDEBAND_GALS_AHB_DBG_SLV_SHFT 0

#define CONN_INFRA_CFG_GALS_CONN2GPS_GALS_DBG_RO_CONN2GPS_CBIP_GALS_SIDEBAND_GALS_AHB_DBG_SLV_ADDR \
	CONN_INFRA_CFG_GALS_CONN2GPS_GALS_DBG_ADDR
#define CONN_INFRA_CFG_GALS_CONN2GPS_GALS_DBG_RO_CONN2GPS_CBIP_GALS_SIDEBAND_GALS_AHB_DBG_SLV_MASK 0xFFFFFFFF
#define CONN_INFRA_CFG_GALS_CONN2GPS_GALS_DBG_RO_CONN2GPS_CBIP_GALS_SIDEBAND_GALS_AHB_DBG_SLV_SHFT 0

#define CONN_INFRA_CFG_GALS_AP2CONN_GALS_DBG_RO_AP2CONN_CBIP_GALS_SIDEBAND_GALS_AXI_DBG_SLV_ADDR \
	CONN_INFRA_CFG_GALS_AP2CONN_GALS_DBG_ADDR
#define CONN_INFRA_CFG_GALS_AP2CONN_GALS_DBG_RO_AP2CONN_CBIP_GALS_SIDEBAND_GALS_AXI_DBG_SLV_MASK 0xFFFFFFFF
#define CONN_INFRA_CFG_GALS_AP2CONN_GALS_DBG_RO_AP2CONN_CBIP_GALS_SIDEBAND_GALS_AXI_DBG_SLV_SHFT 0

#define CONN_INFRA_CFG_GALS_AP2CONN_CTRL_1_R_AP2CONN_CBIP_GALS_SIDEBAND_MST_SYNC_SEL_ADDR \
	CONN_INFRA_CFG_GALS_AP2CONN_CTRL_1_ADDR
#define CONN_INFRA_CFG_GALS_AP2CONN_CTRL_1_R_AP2CONN_CBIP_GALS_SIDEBAND_MST_SYNC_SEL_MASK 0x00000018
#define CONN_INFRA_CFG_GALS_AP2CONN_CTRL_1_R_AP2CONN_CBIP_GALS_SIDEBAND_MST_SYNC_SEL_SHFT 3
#define CONN_INFRA_CFG_GALS_AP2CONN_CTRL_1_R_AP2CONN_CBIP_GALS_SIDEBAND_SLV_SYNC_SEL_ADDR \
	CONN_INFRA_CFG_GALS_AP2CONN_CTRL_1_ADDR
#define CONN_INFRA_CFG_GALS_AP2CONN_CTRL_1_R_AP2CONN_CBIP_GALS_SIDEBAND_SLV_SYNC_SEL_MASK 0x00000006
#define CONN_INFRA_CFG_GALS_AP2CONN_CTRL_1_R_AP2CONN_CBIP_GALS_SIDEBAND_SLV_SYNC_SEL_SHFT 1
#define CONN_INFRA_CFG_GALS_AP2CONN_CTRL_1_R_AP2CONN_CBIP_GALS_SIDEBAND_SAMPLE_SEL_ADDR \
	CONN_INFRA_CFG_GALS_AP2CONN_CTRL_1_ADDR
#define CONN_INFRA_CFG_GALS_AP2CONN_CTRL_1_R_AP2CONN_CBIP_GALS_SIDEBAND_SAMPLE_SEL_MASK 0x00000001
#define CONN_INFRA_CFG_GALS_AP2CONN_CTRL_1_R_AP2CONN_CBIP_GALS_SIDEBAND_SAMPLE_SEL_SHFT 0

#define CONN_INFRA_CFG_GALS_CONN2AP_GALS_DBG_RO_CONN2AP_CBIP_GALS_SIDEBAND_GALS_AXI_DBG_MST_ADDR \
	CONN_INFRA_CFG_GALS_CONN2AP_GALS_DBG_ADDR
#define CONN_INFRA_CFG_GALS_CONN2AP_GALS_DBG_RO_CONN2AP_CBIP_GALS_SIDEBAND_GALS_AXI_DBG_MST_MASK 0xFFFFFFFF
#define CONN_INFRA_CFG_GALS_CONN2AP_GALS_DBG_RO_CONN2AP_CBIP_GALS_SIDEBAND_GALS_AXI_DBG_MST_SHFT 0

#define CONN_INFRA_CFG_GALS_CONN2AP_CTRL_1_R_CONN2AP_CBIP_GALS_SIDEBAND_IN_ARFLUSH_THRE_ADDR \
	CONN_INFRA_CFG_GALS_CONN2AP_CTRL_1_ADDR
#define CONN_INFRA_CFG_GALS_CONN2AP_CTRL_1_R_CONN2AP_CBIP_GALS_SIDEBAND_IN_ARFLUSH_THRE_MASK 0x00000180
#define CONN_INFRA_CFG_GALS_CONN2AP_CTRL_1_R_CONN2AP_CBIP_GALS_SIDEBAND_IN_ARFLUSH_THRE_SHFT 7
#define CONN_INFRA_CFG_GALS_CONN2AP_CTRL_1_R_CONN2AP_CBIP_GALS_SIDEBAND_IN_AWFLUSH_THRE_ADDR \
	CONN_INFRA_CFG_GALS_CONN2AP_CTRL_1_ADDR
#define CONN_INFRA_CFG_GALS_CONN2AP_CTRL_1_R_CONN2AP_CBIP_GALS_SIDEBAND_IN_AWFLUSH_THRE_MASK 0x00000060
#define CONN_INFRA_CFG_GALS_CONN2AP_CTRL_1_R_CONN2AP_CBIP_GALS_SIDEBAND_IN_AWFLUSH_THRE_SHFT 5
#define CONN_INFRA_CFG_GALS_CONN2AP_CTRL_1_R_CONN2AP_CBIP_GALS_SIDEBAND_MST_SYNC_SEL_ADDR \
	CONN_INFRA_CFG_GALS_CONN2AP_CTRL_1_ADDR
#define CONN_INFRA_CFG_GALS_CONN2AP_CTRL_1_R_CONN2AP_CBIP_GALS_SIDEBAND_MST_SYNC_SEL_MASK 0x00000018
#define CONN_INFRA_CFG_GALS_CONN2AP_CTRL_1_R_CONN2AP_CBIP_GALS_SIDEBAND_MST_SYNC_SEL_SHFT 3
#define CONN_INFRA_CFG_GALS_CONN2AP_CTRL_1_R_CONN2AP_CBIP_GALS_SIDEBAND_SLV_SYNC_SEL_ADDR \
	CONN_INFRA_CFG_GALS_CONN2AP_CTRL_1_ADDR
#define CONN_INFRA_CFG_GALS_CONN2AP_CTRL_1_R_CONN2AP_CBIP_GALS_SIDEBAND_SLV_SYNC_SEL_MASK 0x00000006
#define CONN_INFRA_CFG_GALS_CONN2AP_CTRL_1_R_CONN2AP_CBIP_GALS_SIDEBAND_SLV_SYNC_SEL_SHFT 1
#define CONN_INFRA_CFG_GALS_CONN2AP_CTRL_1_R_CONN2AP_CBIP_GALS_SIDEBAND_SAMPLE_SEL_ADDR \
	CONN_INFRA_CFG_GALS_CONN2AP_CTRL_1_ADDR
#define CONN_INFRA_CFG_GALS_CONN2AP_CTRL_1_R_CONN2AP_CBIP_GALS_SIDEBAND_SAMPLE_SEL_MASK 0x00000001
#define CONN_INFRA_CFG_GALS_CONN2AP_CTRL_1_R_CONN2AP_CBIP_GALS_SIDEBAND_SAMPLE_SEL_SHFT 0

#define CONN_INFRA_CFG_GALS_BT2CONN_GALS_DBG_RO_BT2CONN_CBIP_GALS_SIDEBAND_GALS_AXI_DBG_SLV_ADDR \
	CONN_INFRA_CFG_GALS_BT2CONN_GALS_DBG_ADDR
#define CONN_INFRA_CFG_GALS_BT2CONN_GALS_DBG_RO_BT2CONN_CBIP_GALS_SIDEBAND_GALS_AXI_DBG_SLV_MASK 0xFFFFFFFF
#define CONN_INFRA_CFG_GALS_BT2CONN_GALS_DBG_RO_BT2CONN_CBIP_GALS_SIDEBAND_GALS_AXI_DBG_SLV_SHFT 0

#define CONN_INFRA_CFG_GALS_BT2CONN_CTRL_1_RO_BT2CONN_CBIP_GALS_SIDEBAND_SLP_PROT_IDLE_ASYNC_ADDR \
	CONN_INFRA_CFG_GALS_BT2CONN_CTRL_1_ADDR
#define CONN_INFRA_CFG_GALS_BT2CONN_CTRL_1_RO_BT2CONN_CBIP_GALS_SIDEBAND_SLP_PROT_IDLE_ASYNC_MASK 0x00000020
#define CONN_INFRA_CFG_GALS_BT2CONN_CTRL_1_RO_BT2CONN_CBIP_GALS_SIDEBAND_SLP_PROT_IDLE_ASYNC_SHFT 5
#define CONN_INFRA_CFG_GALS_BT2CONN_CTRL_1_R_BT2CONN_CBIP_GALS_SIDEBAND_MST_SYNC_SEL_ADDR \
	CONN_INFRA_CFG_GALS_BT2CONN_CTRL_1_ADDR
#define CONN_INFRA_CFG_GALS_BT2CONN_CTRL_1_R_BT2CONN_CBIP_GALS_SIDEBAND_MST_SYNC_SEL_MASK 0x00000018
#define CONN_INFRA_CFG_GALS_BT2CONN_CTRL_1_R_BT2CONN_CBIP_GALS_SIDEBAND_MST_SYNC_SEL_SHFT 3
#define CONN_INFRA_CFG_GALS_BT2CONN_CTRL_1_R_BT2CONN_CBIP_GALS_SIDEBAND_SLV_SYNC_SEL_ADDR \
	CONN_INFRA_CFG_GALS_BT2CONN_CTRL_1_ADDR
#define CONN_INFRA_CFG_GALS_BT2CONN_CTRL_1_R_BT2CONN_CBIP_GALS_SIDEBAND_SLV_SYNC_SEL_MASK 0x00000006
#define CONN_INFRA_CFG_GALS_BT2CONN_CTRL_1_R_BT2CONN_CBIP_GALS_SIDEBAND_SLV_SYNC_SEL_SHFT 1
#define CONN_INFRA_CFG_GALS_BT2CONN_CTRL_1_R_BT2CONN_CBIP_GALS_SIDEBAND_SAMPLE_SEL_ADDR \
	CONN_INFRA_CFG_GALS_BT2CONN_CTRL_1_ADDR
#define CONN_INFRA_CFG_GALS_BT2CONN_CTRL_1_R_BT2CONN_CBIP_GALS_SIDEBAND_SAMPLE_SEL_MASK 0x00000001
#define CONN_INFRA_CFG_GALS_BT2CONN_CTRL_1_R_BT2CONN_CBIP_GALS_SIDEBAND_SAMPLE_SEL_SHFT 0

#define CONN_INFRA_CFG_GALS_GPS2CONN_GALS_DBG_RO_GPS2CONN_CBIP_GALS_SIDEBAND_GALS_AXI_DBG_SLV_ADDR \
	CONN_INFRA_CFG_GALS_GPS2CONN_GALS_DBG_ADDR
#define CONN_INFRA_CFG_GALS_GPS2CONN_GALS_DBG_RO_GPS2CONN_CBIP_GALS_SIDEBAND_GALS_AXI_DBG_SLV_MASK 0xFFFFFFFF
#define CONN_INFRA_CFG_GALS_GPS2CONN_GALS_DBG_RO_GPS2CONN_CBIP_GALS_SIDEBAND_GALS_AXI_DBG_SLV_SHFT 0

#define CONN_INFRA_CFG_GALS_GPS2CONN_CTRL_1_RO_GPS2CONN_CBIP_GALS_SIDEBAND_SLP_PROT_IDLE_ASYNC_ADDR \
	CONN_INFRA_CFG_GALS_GPS2CONN_CTRL_1_ADDR
#define CONN_INFRA_CFG_GALS_GPS2CONN_CTRL_1_RO_GPS2CONN_CBIP_GALS_SIDEBAND_SLP_PROT_IDLE_ASYNC_MASK 0x00000020
#define CONN_INFRA_CFG_GALS_GPS2CONN_CTRL_1_RO_GPS2CONN_CBIP_GALS_SIDEBAND_SLP_PROT_IDLE_ASYNC_SHFT 5
#define CONN_INFRA_CFG_GALS_GPS2CONN_CTRL_1_R_GPS2CONN_CBIP_GALS_SIDEBAND_MST_SYNC_SEL_ADDR \
	CONN_INFRA_CFG_GALS_GPS2CONN_CTRL_1_ADDR
#define CONN_INFRA_CFG_GALS_GPS2CONN_CTRL_1_R_GPS2CONN_CBIP_GALS_SIDEBAND_MST_SYNC_SEL_MASK 0x00000018
#define CONN_INFRA_CFG_GALS_GPS2CONN_CTRL_1_R_GPS2CONN_CBIP_GALS_SIDEBAND_MST_SYNC_SEL_SHFT 3
#define CONN_INFRA_CFG_GALS_GPS2CONN_CTRL_1_R_GPS2CONN_CBIP_GALS_SIDEBAND_SLV_SYNC_SEL_ADDR \
	CONN_INFRA_CFG_GALS_GPS2CONN_CTRL_1_ADDR
#define CONN_INFRA_CFG_GALS_GPS2CONN_CTRL_1_R_GPS2CONN_CBIP_GALS_SIDEBAND_SLV_SYNC_SEL_MASK 0x00000006
#define CONN_INFRA_CFG_GALS_GPS2CONN_CTRL_1_R_GPS2CONN_CBIP_GALS_SIDEBAND_SLV_SYNC_SEL_SHFT 1
#define CONN_INFRA_CFG_GALS_GPS2CONN_CTRL_1_R_GPS2CONN_CBIP_GALS_SIDEBAND_SAMPLE_SEL_ADDR \
	CONN_INFRA_CFG_GALS_GPS2CONN_CTRL_1_ADDR
#define CONN_INFRA_CFG_GALS_GPS2CONN_CTRL_1_R_GPS2CONN_CBIP_GALS_SIDEBAND_SAMPLE_SEL_MASK 0x00000001
#define CONN_INFRA_CFG_GALS_GPS2CONN_CTRL_1_R_GPS2CONN_CBIP_GALS_SIDEBAND_SAMPLE_SEL_SHFT 0

#define CONN_INFRA_CFG_GALS_CONN2BT_CTRL_1_RO_CONN2BT_CBIP_GALS_SIDEBAND_BRIDGE_IDLE_ASYNC_ADDR \
	CONN_INFRA_CFG_GALS_CONN2BT_CTRL_1_ADDR
#define CONN_INFRA_CFG_GALS_CONN2BT_CTRL_1_RO_CONN2BT_CBIP_GALS_SIDEBAND_BRIDGE_IDLE_ASYNC_MASK 0x00000080
#define CONN_INFRA_CFG_GALS_CONN2BT_CTRL_1_RO_CONN2BT_CBIP_GALS_SIDEBAND_BRIDGE_IDLE_ASYNC_SHFT 7
#define CONN_INFRA_CFG_GALS_CONN2BT_CTRL_1_RO_CONN2BT_CBIP_GALS_SIDEBAND_BRIDGE_IDLE_SYNC_ADDR \
	CONN_INFRA_CFG_GALS_CONN2BT_CTRL_1_ADDR
#define CONN_INFRA_CFG_GALS_CONN2BT_CTRL_1_RO_CONN2BT_CBIP_GALS_SIDEBAND_BRIDGE_IDLE_SYNC_MASK 0x00000040
#define CONN_INFRA_CFG_GALS_CONN2BT_CTRL_1_RO_CONN2BT_CBIP_GALS_SIDEBAND_BRIDGE_IDLE_SYNC_SHFT 6
#define CONN_INFRA_CFG_GALS_CONN2BT_CTRL_1_R_CONN2BT_CBIP_GALS_SIDEBAND_POSTWRITE_DIS_ADDR \
	CONN_INFRA_CFG_GALS_CONN2BT_CTRL_1_ADDR
#define CONN_INFRA_CFG_GALS_CONN2BT_CTRL_1_R_CONN2BT_CBIP_GALS_SIDEBAND_POSTWRITE_DIS_MASK 0x00000020
#define CONN_INFRA_CFG_GALS_CONN2BT_CTRL_1_R_CONN2BT_CBIP_GALS_SIDEBAND_POSTWRITE_DIS_SHFT 5
#define CONN_INFRA_CFG_GALS_CONN2BT_CTRL_1_R_CONN2BT_CBIP_GALS_SIDEBAND_ERROR_FLAG_EN_ADDR \
	CONN_INFRA_CFG_GALS_CONN2BT_CTRL_1_ADDR
#define CONN_INFRA_CFG_GALS_CONN2BT_CTRL_1_R_CONN2BT_CBIP_GALS_SIDEBAND_ERROR_FLAG_EN_MASK 0x00000010
#define CONN_INFRA_CFG_GALS_CONN2BT_CTRL_1_R_CONN2BT_CBIP_GALS_SIDEBAND_ERROR_FLAG_EN_SHFT 4
#define CONN_INFRA_CFG_GALS_CONN2BT_CTRL_1_R_CONN2BT_CBIP_GALS_SIDEBAND_MONITOR_MODE_ADDR \
	CONN_INFRA_CFG_GALS_CONN2BT_CTRL_1_ADDR
#define CONN_INFRA_CFG_GALS_CONN2BT_CTRL_1_R_CONN2BT_CBIP_GALS_SIDEBAND_MONITOR_MODE_MASK 0x00000008
#define CONN_INFRA_CFG_GALS_CONN2BT_CTRL_1_R_CONN2BT_CBIP_GALS_SIDEBAND_MONITOR_MODE_SHFT 3
#define CONN_INFRA_CFG_GALS_CONN2BT_CTRL_1_R_CONN2BT_CBIP_GALS_SIDEBAND_CMD_CNT_CLR_ADDR \
	CONN_INFRA_CFG_GALS_CONN2BT_CTRL_1_ADDR
#define CONN_INFRA_CFG_GALS_CONN2BT_CTRL_1_R_CONN2BT_CBIP_GALS_SIDEBAND_CMD_CNT_CLR_MASK 0x00000004
#define CONN_INFRA_CFG_GALS_CONN2BT_CTRL_1_R_CONN2BT_CBIP_GALS_SIDEBAND_CMD_CNT_CLR_SHFT 2
#define CONN_INFRA_CFG_GALS_CONN2BT_CTRL_1_R_CONN2BT_CBIP_GALS_SIDEBAND_AFIFO_SYNC_SEL_ADDR \
	CONN_INFRA_CFG_GALS_CONN2BT_CTRL_1_ADDR
#define CONN_INFRA_CFG_GALS_CONN2BT_CTRL_1_R_CONN2BT_CBIP_GALS_SIDEBAND_AFIFO_SYNC_SEL_MASK 0x00000003
#define CONN_INFRA_CFG_GALS_CONN2BT_CTRL_1_R_CONN2BT_CBIP_GALS_SIDEBAND_AFIFO_SYNC_SEL_SHFT 0

#define CONN_INFRA_CFG_GALS_CONN2GPS_CTRL_1_RO_CONN2GPS_CBIP_GALS_SIDEBAND_BRIDGE_IDLE_ASYNC_ADDR \
	CONN_INFRA_CFG_GALS_CONN2GPS_CTRL_1_ADDR
#define CONN_INFRA_CFG_GALS_CONN2GPS_CTRL_1_RO_CONN2GPS_CBIP_GALS_SIDEBAND_BRIDGE_IDLE_ASYNC_MASK 0x00000080
#define CONN_INFRA_CFG_GALS_CONN2GPS_CTRL_1_RO_CONN2GPS_CBIP_GALS_SIDEBAND_BRIDGE_IDLE_ASYNC_SHFT 7
#define CONN_INFRA_CFG_GALS_CONN2GPS_CTRL_1_RO_CONN2GPS_CBIP_GALS_SIDEBAND_BRIDGE_IDLE_SYNC_ADDR \
	CONN_INFRA_CFG_GALS_CONN2GPS_CTRL_1_ADDR
#define CONN_INFRA_CFG_GALS_CONN2GPS_CTRL_1_RO_CONN2GPS_CBIP_GALS_SIDEBAND_BRIDGE_IDLE_SYNC_MASK 0x00000040
#define CONN_INFRA_CFG_GALS_CONN2GPS_CTRL_1_RO_CONN2GPS_CBIP_GALS_SIDEBAND_BRIDGE_IDLE_SYNC_SHFT 6
#define CONN_INFRA_CFG_GALS_CONN2GPS_CTRL_1_R_CONN2GPS_CBIP_GALS_SIDEBAND_POSTWRITE_DIS_ADDR \
	CONN_INFRA_CFG_GALS_CONN2GPS_CTRL_1_ADDR
#define CONN_INFRA_CFG_GALS_CONN2GPS_CTRL_1_R_CONN2GPS_CBIP_GALS_SIDEBAND_POSTWRITE_DIS_MASK 0x00000020
#define CONN_INFRA_CFG_GALS_CONN2GPS_CTRL_1_R_CONN2GPS_CBIP_GALS_SIDEBAND_POSTWRITE_DIS_SHFT 5
#define CONN_INFRA_CFG_GALS_CONN2GPS_CTRL_1_R_CONN2GPS_CBIP_GALS_SIDEBAND_ERROR_FLAG_EN_ADDR \
	CONN_INFRA_CFG_GALS_CONN2GPS_CTRL_1_ADDR
#define CONN_INFRA_CFG_GALS_CONN2GPS_CTRL_1_R_CONN2GPS_CBIP_GALS_SIDEBAND_ERROR_FLAG_EN_MASK 0x00000010
#define CONN_INFRA_CFG_GALS_CONN2GPS_CTRL_1_R_CONN2GPS_CBIP_GALS_SIDEBAND_ERROR_FLAG_EN_SHFT 4
#define CONN_INFRA_CFG_GALS_CONN2GPS_CTRL_1_R_CONN2GPS_CBIP_GALS_SIDEBAND_MONITOR_MODE_ADDR \
	CONN_INFRA_CFG_GALS_CONN2GPS_CTRL_1_ADDR
#define CONN_INFRA_CFG_GALS_CONN2GPS_CTRL_1_R_CONN2GPS_CBIP_GALS_SIDEBAND_MONITOR_MODE_MASK 0x00000008
#define CONN_INFRA_CFG_GALS_CONN2GPS_CTRL_1_R_CONN2GPS_CBIP_GALS_SIDEBAND_MONITOR_MODE_SHFT 3
#define CONN_INFRA_CFG_GALS_CONN2GPS_CTRL_1_R_CONN2GPS_CBIP_GALS_SIDEBAND_CMD_CNT_CLR_ADDR \
	CONN_INFRA_CFG_GALS_CONN2GPS_CTRL_1_ADDR
#define CONN_INFRA_CFG_GALS_CONN2GPS_CTRL_1_R_CONN2GPS_CBIP_GALS_SIDEBAND_CMD_CNT_CLR_MASK 0x00000004
#define CONN_INFRA_CFG_GALS_CONN2GPS_CTRL_1_R_CONN2GPS_CBIP_GALS_SIDEBAND_CMD_CNT_CLR_SHFT 2
#define CONN_INFRA_CFG_GALS_CONN2GPS_CTRL_1_R_CONN2GPS_CBIP_GALS_SIDEBAND_AFIFO_SYNC_SEL_ADDR \
	CONN_INFRA_CFG_GALS_CONN2GPS_CTRL_1_ADDR
#define CONN_INFRA_CFG_GALS_CONN2GPS_CTRL_1_R_CONN2GPS_CBIP_GALS_SIDEBAND_AFIFO_SYNC_SEL_MASK 0x00000003
#define CONN_INFRA_CFG_GALS_CONN2GPS_CTRL_1_R_CONN2GPS_CBIP_GALS_SIDEBAND_AFIFO_SYNC_SEL_SHFT 0

#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_R_CONN2AP_TX_BIST_EN_ADDR CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_ADDR
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_R_CONN2AP_TX_BIST_EN_MASK 0x00000001
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_R_CONN2AP_TX_BIST_EN_SHFT 0
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_R_CONN2AP_TX_BIST_AWID_EN_ADDR CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_ADDR
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_R_CONN2AP_TX_BIST_AWID_EN_MASK 0x0000000C
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_R_CONN2AP_TX_BIST_AWID_EN_SHFT 2
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_R_CONN2AP_TX_BIST_AWLEN_EN_ADDR CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_ADDR
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_R_CONN2AP_TX_BIST_AWLEN_EN_MASK 0x00000030
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_R_CONN2AP_TX_BIST_AWLEN_EN_SHFT 4
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_R_CONN2AP_TX_BIST_AWADDR_EN_ADDR CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_ADDR
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_R_CONN2AP_TX_BIST_AWADDR_EN_MASK 0x000000C0
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_R_CONN2AP_TX_BIST_AWADDR_EN_SHFT 6
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_R_CONN2AP_TX_BIST_AWSIZE_EN_ADDR CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_ADDR
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_R_CONN2AP_TX_BIST_AWSIZE_EN_MASK 0x00000300
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_R_CONN2AP_TX_BIST_AWSIZE_EN_SHFT 8
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_R_CONN2AP_TX_BIST_AWBURST_EN_ADDR CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_ADDR
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_R_CONN2AP_TX_BIST_AWBURST_EN_MASK 0x00000C00
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_R_CONN2AP_TX_BIST_AWBURST_EN_SHFT 10
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_R_CONN2AP_TX_BIST_AWCACHE_EN_ADDR CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_ADDR
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_R_CONN2AP_TX_BIST_AWCACHE_EN_MASK 0x00003000
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_R_CONN2AP_TX_BIST_AWCACHE_EN_SHFT 12
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_R_CONN2AP_TX_BIST_AWPROT_EN_ADDR CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_ADDR
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_R_CONN2AP_TX_BIST_AWPROT_EN_MASK 0x0000C000
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_R_CONN2AP_TX_BIST_AWPROT_EN_SHFT 14
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_R_CONN2AP_TX_BIST_AWUSER_EN_ADDR CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_ADDR
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_R_CONN2AP_TX_BIST_AWUSER_EN_MASK 0x00030000
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_R_CONN2AP_TX_BIST_AWUSER_EN_SHFT 16
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_R_CONN2AP_TX_BIST_AWDOMAIN_APC_EN_ADDR \
	CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_ADDR
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_R_CONN2AP_TX_BIST_AWDOMAIN_APC_EN_MASK 0x000C0000
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_R_CONN2AP_TX_BIST_AWDOMAIN_APC_EN_SHFT 18
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_R_CONN2AP_TX_BIST_AWULTRAL_EN_ADDR CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_ADDR
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_R_CONN2AP_TX_BIST_AWULTRAL_EN_MASK 0x00300000
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_R_CONN2AP_TX_BIST_AWULTRAL_EN_SHFT 20
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_R_CONN2AP_TX_BIST_ARID_EN_ADDR CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_ADDR
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_R_CONN2AP_TX_BIST_ARID_EN_MASK 0x00C00000
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_R_CONN2AP_TX_BIST_ARID_EN_SHFT 22
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_R_CONN2AP_TX_BIST_ARLEN_EN_ADDR CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_ADDR
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_R_CONN2AP_TX_BIST_ARLEN_EN_MASK 0x03000000
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_R_CONN2AP_TX_BIST_ARLEN_EN_SHFT 24
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_R_CONN2AP_TX_BIST_ARADDR_EN_ADDR CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_ADDR
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_R_CONN2AP_TX_BIST_ARADDR_EN_MASK 0x0C000000
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_R_CONN2AP_TX_BIST_ARADDR_EN_SHFT 26
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_R_CONN2AP_TX_BIST_ARSIZE_EN_ADDR CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_ADDR
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_R_CONN2AP_TX_BIST_ARSIZE_EN_MASK 0x30000000
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_R_CONN2AP_TX_BIST_ARSIZE_EN_SHFT 28
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_R_CONN2AP_TX_BIST_ARBURST_EN_ADDR CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_ADDR
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_R_CONN2AP_TX_BIST_ARBURST_EN_MASK 0xC0000000
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_0_R_CONN2AP_TX_BIST_ARBURST_EN_SHFT 30

#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_1_R_CONN2AP_TX_BIST_ARCACHE_EN_ADDR CONN_INFRA_CFG_BIST_CONN2AP_CTRL_1_ADDR
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_1_R_CONN2AP_TX_BIST_ARCACHE_EN_MASK 0x00000003
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_1_R_CONN2AP_TX_BIST_ARCACHE_EN_SHFT 0
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_1_R_CONN2AP_TX_BIST_ARPROT_EN_ADDR CONN_INFRA_CFG_BIST_CONN2AP_CTRL_1_ADDR
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_1_R_CONN2AP_TX_BIST_ARPROT_EN_MASK 0x0000000C
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_1_R_CONN2AP_TX_BIST_ARPROT_EN_SHFT 2
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_1_R_CONN2AP_TX_BIST_ARUSER_EN_ADDR CONN_INFRA_CFG_BIST_CONN2AP_CTRL_1_ADDR
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_1_R_CONN2AP_TX_BIST_ARUSER_EN_MASK 0x00000030
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_1_R_CONN2AP_TX_BIST_ARUSER_EN_SHFT 4
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_1_R_CONN2AP_TX_BIST_ARDOMAIN_APC_EN_ADDR \
	CONN_INFRA_CFG_BIST_CONN2AP_CTRL_1_ADDR
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_1_R_CONN2AP_TX_BIST_ARDOMAIN_APC_EN_MASK 0x000000C0
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_1_R_CONN2AP_TX_BIST_ARDOMAIN_APC_EN_SHFT 6
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_1_R_CONN2AP_TX_BIST_ARULTRA_EN_ADDR CONN_INFRA_CFG_BIST_CONN2AP_CTRL_1_ADDR
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_1_R_CONN2AP_TX_BIST_ARULTRA_EN_MASK 0x00000300
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_1_R_CONN2AP_TX_BIST_ARULTRA_EN_SHFT 8
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_1_R_CONN2AP_TX_BIST_WDATA_EN_ADDR CONN_INFRA_CFG_BIST_CONN2AP_CTRL_1_ADDR
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_1_R_CONN2AP_TX_BIST_WDATA_EN_MASK 0x00000C00
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_1_R_CONN2AP_TX_BIST_WDATA_EN_SHFT 10
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_1_R_CONN2AP_TX_BIST_WSTRB_EN_ADDR CONN_INFRA_CFG_BIST_CONN2AP_CTRL_1_ADDR
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_1_R_CONN2AP_TX_BIST_WSTRB_EN_MASK 0x00003000
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_1_R_CONN2AP_TX_BIST_WSTRB_EN_SHFT 12
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_1_R_CONN2AP_TX_BIST_BRESP_EN_ADDR CONN_INFRA_CFG_BIST_CONN2AP_CTRL_1_ADDR
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_1_R_CONN2AP_TX_BIST_BRESP_EN_MASK 0x0000C000
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_1_R_CONN2AP_TX_BIST_BRESP_EN_SHFT 14
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_1_R_CONN2AP_TX_BIST_RDATA_EN_ADDR CONN_INFRA_CFG_BIST_CONN2AP_CTRL_1_ADDR
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_1_R_CONN2AP_TX_BIST_RDATA_EN_MASK 0x00030000
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_1_R_CONN2AP_TX_BIST_RDATA_EN_SHFT 16
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_1_R_CONN2AP_TX_BIST_RRESP_EN_ADDR CONN_INFRA_CFG_BIST_CONN2AP_CTRL_1_ADDR
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_1_R_CONN2AP_TX_BIST_RRESP_EN_MASK 0x000C0000
#define CONN_INFRA_CFG_BIST_CONN2AP_CTRL_1_R_CONN2AP_TX_BIST_RRESP_EN_SHFT 18

#define CONN_INFRA_CFG_PCIE2AP_REMAP_0_R_PCIE2AP_PUBLIC_REMAPPING_1_ADDR CONN_INFRA_CFG_PCIE2AP_REMAP_0_ADDR
#define CONN_INFRA_CFG_PCIE2AP_REMAP_0_R_PCIE2AP_PUBLIC_REMAPPING_1_MASK 0xFFFF0000
#define CONN_INFRA_CFG_PCIE2AP_REMAP_0_R_PCIE2AP_PUBLIC_REMAPPING_1_SHFT 16
#define CONN_INFRA_CFG_PCIE2AP_REMAP_0_R_PCIE2AP_PUBLIC_REMAPPING_0_ADDR CONN_INFRA_CFG_PCIE2AP_REMAP_0_ADDR
#define CONN_INFRA_CFG_PCIE2AP_REMAP_0_R_PCIE2AP_PUBLIC_REMAPPING_0_MASK 0x0000FFFF
#define CONN_INFRA_CFG_PCIE2AP_REMAP_0_R_PCIE2AP_PUBLIC_REMAPPING_0_SHFT 0

#define CONN_INFRA_CFG_PCIE2AP_REMAP_1_R_PCIE2AP_PUBLIC_REMAPPING_3_ADDR CONN_INFRA_CFG_PCIE2AP_REMAP_1_ADDR
#define CONN_INFRA_CFG_PCIE2AP_REMAP_1_R_PCIE2AP_PUBLIC_REMAPPING_3_MASK 0xFFFF0000
#define CONN_INFRA_CFG_PCIE2AP_REMAP_1_R_PCIE2AP_PUBLIC_REMAPPING_3_SHFT 16
#define CONN_INFRA_CFG_PCIE2AP_REMAP_1_R_PCIE2AP_PUBLIC_REMAPPING_2_ADDR CONN_INFRA_CFG_PCIE2AP_REMAP_1_ADDR
#define CONN_INFRA_CFG_PCIE2AP_REMAP_1_R_PCIE2AP_PUBLIC_REMAPPING_2_MASK 0x0000FFFF
#define CONN_INFRA_CFG_PCIE2AP_REMAP_1_R_PCIE2AP_PUBLIC_REMAPPING_2_SHFT 0

#define CONN_INFRA_CFG_PCIE2AP_REMAP_2_R_PCIE2AP_PUBLIC_REMAPPING_5_ADDR CONN_INFRA_CFG_PCIE2AP_REMAP_2_ADDR
#define CONN_INFRA_CFG_PCIE2AP_REMAP_2_R_PCIE2AP_PUBLIC_REMAPPING_5_MASK 0xFFFF0000
#define CONN_INFRA_CFG_PCIE2AP_REMAP_2_R_PCIE2AP_PUBLIC_REMAPPING_5_SHFT 16
#define CONN_INFRA_CFG_PCIE2AP_REMAP_2_R_PCIE2AP_PUBLIC_REMAPPING_4_ADDR CONN_INFRA_CFG_PCIE2AP_REMAP_2_ADDR
#define CONN_INFRA_CFG_PCIE2AP_REMAP_2_R_PCIE2AP_PUBLIC_REMAPPING_4_MASK 0x0000FFFF
#define CONN_INFRA_CFG_PCIE2AP_REMAP_2_R_PCIE2AP_PUBLIC_REMAPPING_4_SHFT 0

#define CONN_INFRA_CFG_PCIE2AP_REMAP_3_R_PCIE2AP_PUBLIC_REMAPPING_7_ADDR CONN_INFRA_CFG_PCIE2AP_REMAP_3_ADDR
#define CONN_INFRA_CFG_PCIE2AP_REMAP_3_R_PCIE2AP_PUBLIC_REMAPPING_7_MASK 0xFFFF0000
#define CONN_INFRA_CFG_PCIE2AP_REMAP_3_R_PCIE2AP_PUBLIC_REMAPPING_7_SHFT 16
#define CONN_INFRA_CFG_PCIE2AP_REMAP_3_R_PCIE2AP_PUBLIC_REMAPPING_6_ADDR CONN_INFRA_CFG_PCIE2AP_REMAP_3_ADDR
#define CONN_INFRA_CFG_PCIE2AP_REMAP_3_R_PCIE2AP_PUBLIC_REMAPPING_6_MASK 0x0000FFFF
#define CONN_INFRA_CFG_PCIE2AP_REMAP_3_R_PCIE2AP_PUBLIC_REMAPPING_6_SHFT 0

#define CONN_INFRA_CFG_PCIE2AP_REMAP_4_R_PCIE2AP_PUBLIC_REMAPPING_9_ADDR CONN_INFRA_CFG_PCIE2AP_REMAP_4_ADDR
#define CONN_INFRA_CFG_PCIE2AP_REMAP_4_R_PCIE2AP_PUBLIC_REMAPPING_9_MASK 0xFFFF0000
#define CONN_INFRA_CFG_PCIE2AP_REMAP_4_R_PCIE2AP_PUBLIC_REMAPPING_9_SHFT 16
#define CONN_INFRA_CFG_PCIE2AP_REMAP_4_R_PCIE2AP_PUBLIC_REMAPPING_8_ADDR CONN_INFRA_CFG_PCIE2AP_REMAP_4_ADDR
#define CONN_INFRA_CFG_PCIE2AP_REMAP_4_R_PCIE2AP_PUBLIC_REMAPPING_8_MASK 0x0000FFFF
#define CONN_INFRA_CFG_PCIE2AP_REMAP_4_R_PCIE2AP_PUBLIC_REMAPPING_8_SHFT 0

#define CONN_INFRA_CFG_PCIE2AP_REMAP_5_R_PCIE2AP_PUBLIC_REMAPPING_B_ADDR CONN_INFRA_CFG_PCIE2AP_REMAP_5_ADDR
#define CONN_INFRA_CFG_PCIE2AP_REMAP_5_R_PCIE2AP_PUBLIC_REMAPPING_B_MASK 0xFFFF0000
#define CONN_INFRA_CFG_PCIE2AP_REMAP_5_R_PCIE2AP_PUBLIC_REMAPPING_B_SHFT 16
#define CONN_INFRA_CFG_PCIE2AP_REMAP_5_R_PCIE2AP_PUBLIC_REMAPPING_A_ADDR CONN_INFRA_CFG_PCIE2AP_REMAP_5_ADDR
#define CONN_INFRA_CFG_PCIE2AP_REMAP_5_R_PCIE2AP_PUBLIC_REMAPPING_A_MASK 0x0000FFFF
#define CONN_INFRA_CFG_PCIE2AP_REMAP_5_R_PCIE2AP_PUBLIC_REMAPPING_A_SHFT 0

#define CONN_INFRA_CFG_PCIE2AP_REMAP_6_R_PCIE2AP_PUBLIC_REMAPPING_D_ADDR CONN_INFRA_CFG_PCIE2AP_REMAP_6_ADDR
#define CONN_INFRA_CFG_PCIE2AP_REMAP_6_R_PCIE2AP_PUBLIC_REMAPPING_D_MASK 0xFFFF0000
#define CONN_INFRA_CFG_PCIE2AP_REMAP_6_R_PCIE2AP_PUBLIC_REMAPPING_D_SHFT 16
#define CONN_INFRA_CFG_PCIE2AP_REMAP_6_R_PCIE2AP_PUBLIC_REMAPPING_C_ADDR CONN_INFRA_CFG_PCIE2AP_REMAP_6_ADDR
#define CONN_INFRA_CFG_PCIE2AP_REMAP_6_R_PCIE2AP_PUBLIC_REMAPPING_C_MASK 0x0000FFFF
#define CONN_INFRA_CFG_PCIE2AP_REMAP_6_R_PCIE2AP_PUBLIC_REMAPPING_C_SHFT 0

#define CONN_INFRA_CFG_PCIE2AP_REMAP_7_R_PCIE2AP_PUBLIC_REMAPPING_F_ADDR CONN_INFRA_CFG_PCIE2AP_REMAP_7_ADDR
#define CONN_INFRA_CFG_PCIE2AP_REMAP_7_R_PCIE2AP_PUBLIC_REMAPPING_F_MASK 0xFFFF0000
#define CONN_INFRA_CFG_PCIE2AP_REMAP_7_R_PCIE2AP_PUBLIC_REMAPPING_F_SHFT 16
#define CONN_INFRA_CFG_PCIE2AP_REMAP_7_R_PCIE2AP_PUBLIC_REMAPPING_E_ADDR CONN_INFRA_CFG_PCIE2AP_REMAP_7_ADDR
#define CONN_INFRA_CFG_PCIE2AP_REMAP_7_R_PCIE2AP_PUBLIC_REMAPPING_E_MASK 0x0000FFFF
#define CONN_INFRA_CFG_PCIE2AP_REMAP_7_R_PCIE2AP_PUBLIC_REMAPPING_E_SHFT 0

#define CONN_INFRA_CFG_LEGACY_REMAP_CTRL_0_R_CONNAC_LEGACY_AP2WF_ADDR_MAP0_ADDR CONN_INFRA_CFG_LEGACY_REMAP_CTRL_0_ADDR
#define CONN_INFRA_CFG_LEGACY_REMAP_CTRL_0_R_CONNAC_LEGACY_AP2WF_ADDR_MAP0_MASK 0x000FFFFF
#define CONN_INFRA_CFG_LEGACY_REMAP_CTRL_0_R_CONNAC_LEGACY_AP2WF_ADDR_MAP0_SHFT 0

#define CONN_INFRA_CFG_LEGACY_REMAP_CTRL_1_R_CONNAC_LEGACY_AP2WF_ADDR_MAP1_ADDR CONN_INFRA_CFG_LEGACY_REMAP_CTRL_1_ADDR
#define CONN_INFRA_CFG_LEGACY_REMAP_CTRL_1_R_CONNAC_LEGACY_AP2WF_ADDR_MAP1_MASK 0x000FFFFF
#define CONN_INFRA_CFG_LEGACY_REMAP_CTRL_1_R_CONNAC_LEGACY_AP2WF_ADDR_MAP1_SHFT 0

#define CONN_INFRA_CFG_LEGACY_REMAP_CTRL_2_R_CONNAC_LEGACY_AP2WF_ADDR_MAP3_ADDR CONN_INFRA_CFG_LEGACY_REMAP_CTRL_2_ADDR
#define CONN_INFRA_CFG_LEGACY_REMAP_CTRL_2_R_CONNAC_LEGACY_AP2WF_ADDR_MAP3_MASK 0xFFFF0000
#define CONN_INFRA_CFG_LEGACY_REMAP_CTRL_2_R_CONNAC_LEGACY_AP2WF_ADDR_MAP3_SHFT 16
#define CONN_INFRA_CFG_LEGACY_REMAP_CTRL_2_R_CONNAC_LEGACY_AP2WF_ADDR_MAP2_ADDR CONN_INFRA_CFG_LEGACY_REMAP_CTRL_2_ADDR
#define CONN_INFRA_CFG_LEGACY_REMAP_CTRL_2_R_CONNAC_LEGACY_AP2WF_ADDR_MAP2_MASK 0x0000FFFF
#define CONN_INFRA_CFG_LEGACY_REMAP_CTRL_2_R_CONNAC_LEGACY_AP2WF_ADDR_MAP2_SHFT 0

#define CONN_INFRA_CFG_LEGACY_REMAP_CTRL_3_R_CONNAC_LEGACY_AP2WF_ADDR_MAP5_ADDR CONN_INFRA_CFG_LEGACY_REMAP_CTRL_3_ADDR
#define CONN_INFRA_CFG_LEGACY_REMAP_CTRL_3_R_CONNAC_LEGACY_AP2WF_ADDR_MAP5_MASK 0xFFFF0000
#define CONN_INFRA_CFG_LEGACY_REMAP_CTRL_3_R_CONNAC_LEGACY_AP2WF_ADDR_MAP5_SHFT 16
#define CONN_INFRA_CFG_LEGACY_REMAP_CTRL_3_R_CONNAC_LEGACY_AP2WF_ADDR_MAP4_ADDR CONN_INFRA_CFG_LEGACY_REMAP_CTRL_3_ADDR
#define CONN_INFRA_CFG_LEGACY_REMAP_CTRL_3_R_CONNAC_LEGACY_AP2WF_ADDR_MAP4_MASK 0x0000FFFF
#define CONN_INFRA_CFG_LEGACY_REMAP_CTRL_3_R_CONNAC_LEGACY_AP2WF_ADDR_MAP4_SHFT 0

#define CONN_INFRA_CFG_LEGACY_REMAP_CTRL_4_R_CONNAC_LEGACY_AP2WF_ADDR_MAP7_ADDR CONN_INFRA_CFG_LEGACY_REMAP_CTRL_4_ADDR
#define CONN_INFRA_CFG_LEGACY_REMAP_CTRL_4_R_CONNAC_LEGACY_AP2WF_ADDR_MAP7_MASK 0xFFFF0000
#define CONN_INFRA_CFG_LEGACY_REMAP_CTRL_4_R_CONNAC_LEGACY_AP2WF_ADDR_MAP7_SHFT 16
#define CONN_INFRA_CFG_LEGACY_REMAP_CTRL_4_R_CONNAC_LEGACY_AP2WF_ADDR_MAP6_ADDR CONN_INFRA_CFG_LEGACY_REMAP_CTRL_4_ADDR
#define CONN_INFRA_CFG_LEGACY_REMAP_CTRL_4_R_CONNAC_LEGACY_AP2WF_ADDR_MAP6_MASK 0x0000FFFF
#define CONN_INFRA_CFG_LEGACY_REMAP_CTRL_4_R_CONNAC_LEGACY_AP2WF_ADDR_MAP6_SHFT 0

#define CONN_INFRA_CFG_LEGACY_REMAP_CTRL_5_R_CONNAC_LEGACY_AP2WF_ADDR_MAP9_ADDR CONN_INFRA_CFG_LEGACY_REMAP_CTRL_5_ADDR
#define CONN_INFRA_CFG_LEGACY_REMAP_CTRL_5_R_CONNAC_LEGACY_AP2WF_ADDR_MAP9_MASK 0xFFFF0000
#define CONN_INFRA_CFG_LEGACY_REMAP_CTRL_5_R_CONNAC_LEGACY_AP2WF_ADDR_MAP9_SHFT 16
#define CONN_INFRA_CFG_LEGACY_REMAP_CTRL_5_R_CONNAC_LEGACY_AP2WF_ADDR_MAP8_ADDR CONN_INFRA_CFG_LEGACY_REMAP_CTRL_5_ADDR
#define CONN_INFRA_CFG_LEGACY_REMAP_CTRL_5_R_CONNAC_LEGACY_AP2WF_ADDR_MAP8_MASK 0x0000FFFF
#define CONN_INFRA_CFG_LEGACY_REMAP_CTRL_5_R_CONNAC_LEGACY_AP2WF_ADDR_MAP8_SHFT 0

#define CONN_INFRA_CFG_LEGACY_REMAP_CTRL_6_R_CONNAC_LEGACY_AP2WF_MAPPER_ENABLE_ADDR \
	CONN_INFRA_CFG_LEGACY_REMAP_CTRL_6_ADDR
#define CONN_INFRA_CFG_LEGACY_REMAP_CTRL_6_R_CONNAC_LEGACY_AP2WF_MAPPER_ENABLE_MASK 0x00000002
#define CONN_INFRA_CFG_LEGACY_REMAP_CTRL_6_R_CONNAC_LEGACY_AP2WF_MAPPER_ENABLE_SHFT 1
#define CONN_INFRA_CFG_LEGACY_REMAP_CTRL_6_R_CONNAC_LEGACY_AP2BGF_MAPPER_ENABLE_ADDR \
	CONN_INFRA_CFG_LEGACY_REMAP_CTRL_6_ADDR
#define CONN_INFRA_CFG_LEGACY_REMAP_CTRL_6_R_CONNAC_LEGACY_AP2BGF_MAPPER_ENABLE_MASK 0x00000001
#define CONN_INFRA_CFG_LEGACY_REMAP_CTRL_6_R_CONNAC_LEGACY_AP2BGF_MAPPER_ENABLE_SHFT 0

#define CONN_INFRA_CFG_WF_LIGHT_SECURITY_START_ADDR_0_R_WF_LIGHT_SECURITY_START_ADDR_0_ADDR \
	CONN_INFRA_CFG_WF_LIGHT_SECURITY_START_ADDR_0_ADDR
#define CONN_INFRA_CFG_WF_LIGHT_SECURITY_START_ADDR_0_R_WF_LIGHT_SECURITY_START_ADDR_0_MASK 0xFFFFFFFF
#define CONN_INFRA_CFG_WF_LIGHT_SECURITY_START_ADDR_0_R_WF_LIGHT_SECURITY_START_ADDR_0_SHFT 0

#define CONN_INFRA_CFG_WF_LIGHT_SECURITY_END_ADDR_0_R_WF_LIGHT_SECURITY_END_ADDR_0_ADDR \
	CONN_INFRA_CFG_WF_LIGHT_SECURITY_END_ADDR_0_ADDR
#define CONN_INFRA_CFG_WF_LIGHT_SECURITY_END_ADDR_0_R_WF_LIGHT_SECURITY_END_ADDR_0_MASK 0xFFFFFFFF
#define CONN_INFRA_CFG_WF_LIGHT_SECURITY_END_ADDR_0_R_WF_LIGHT_SECURITY_END_ADDR_0_SHFT 0

#define CONN_INFRA_CFG_WF_LIGHT_SECURITY_START_ADDR_1_R_WF_LIGHT_SECURITY_START_ADDR_1_ADDR \
	CONN_INFRA_CFG_WF_LIGHT_SECURITY_START_ADDR_1_ADDR
#define CONN_INFRA_CFG_WF_LIGHT_SECURITY_START_ADDR_1_R_WF_LIGHT_SECURITY_START_ADDR_1_MASK 0xFFFFFFFF
#define CONN_INFRA_CFG_WF_LIGHT_SECURITY_START_ADDR_1_R_WF_LIGHT_SECURITY_START_ADDR_1_SHFT 0

#define CONN_INFRA_CFG_WF_LIGHT_SECURITY_END_ADDR_1_R_WF_LIGHT_SECURITY_END_ADDR_1_ADDR \
	CONN_INFRA_CFG_WF_LIGHT_SECURITY_END_ADDR_1_ADDR
#define CONN_INFRA_CFG_WF_LIGHT_SECURITY_END_ADDR_1_R_WF_LIGHT_SECURITY_END_ADDR_1_MASK 0xFFFFFFFF
#define CONN_INFRA_CFG_WF_LIGHT_SECURITY_END_ADDR_1_R_WF_LIGHT_SECURITY_END_ADDR_1_SHFT 0

#define CONN_INFRA_CFG_WF_LIGHT_SECURITY_START_ADDR_2_R_WF_LIGHT_SECURITY_START_ADDR_2_ADDR \
	CONN_INFRA_CFG_WF_LIGHT_SECURITY_START_ADDR_2_ADDR
#define CONN_INFRA_CFG_WF_LIGHT_SECURITY_START_ADDR_2_R_WF_LIGHT_SECURITY_START_ADDR_2_MASK 0xFFFFFFFF
#define CONN_INFRA_CFG_WF_LIGHT_SECURITY_START_ADDR_2_R_WF_LIGHT_SECURITY_START_ADDR_2_SHFT 0

#define CONN_INFRA_CFG_WF_LIGHT_SECURITY_END_ADDR_2_R_WF_LIGHT_SECURITY_END_ADDR_2_ADDR \
	CONN_INFRA_CFG_WF_LIGHT_SECURITY_END_ADDR_2_ADDR
#define CONN_INFRA_CFG_WF_LIGHT_SECURITY_END_ADDR_2_R_WF_LIGHT_SECURITY_END_ADDR_2_MASK 0xFFFFFFFF
#define CONN_INFRA_CFG_WF_LIGHT_SECURITY_END_ADDR_2_R_WF_LIGHT_SECURITY_END_ADDR_2_SHFT 0

#define CONN_INFRA_CFG_BT_LIGHT_SECURITY_START_ADDR_0_R_BT_LIGHT_SECURITY_START_ADDR_0_ADDR \
	CONN_INFRA_CFG_BT_LIGHT_SECURITY_START_ADDR_0_ADDR
#define CONN_INFRA_CFG_BT_LIGHT_SECURITY_START_ADDR_0_R_BT_LIGHT_SECURITY_START_ADDR_0_MASK 0xFFFFFFFF
#define CONN_INFRA_CFG_BT_LIGHT_SECURITY_START_ADDR_0_R_BT_LIGHT_SECURITY_START_ADDR_0_SHFT 0

#define CONN_INFRA_CFG_BT_LIGHT_SECURITY_END_ADDR_0_R_BT_LIGHT_SECURITY_END_ADDR_0_ADDR \
	CONN_INFRA_CFG_BT_LIGHT_SECURITY_END_ADDR_0_ADDR
#define CONN_INFRA_CFG_BT_LIGHT_SECURITY_END_ADDR_0_R_BT_LIGHT_SECURITY_END_ADDR_0_MASK 0xFFFFFFFF
#define CONN_INFRA_CFG_BT_LIGHT_SECURITY_END_ADDR_0_R_BT_LIGHT_SECURITY_END_ADDR_0_SHFT 0

#define CONN_INFRA_CFG_BT_LIGHT_SECURITY_START_ADDR_1_R_BT_LIGHT_SECURITY_START_ADDR_1_ADDR \
	CONN_INFRA_CFG_BT_LIGHT_SECURITY_START_ADDR_1_ADDR
#define CONN_INFRA_CFG_BT_LIGHT_SECURITY_START_ADDR_1_R_BT_LIGHT_SECURITY_START_ADDR_1_MASK 0xFFFFFFFF
#define CONN_INFRA_CFG_BT_LIGHT_SECURITY_START_ADDR_1_R_BT_LIGHT_SECURITY_START_ADDR_1_SHFT 0

#define CONN_INFRA_CFG_BT_LIGHT_SECURITY_END_ADDR_1_R_BT_LIGHT_SECURITY_END_ADDR_1_ADDR \
	CONN_INFRA_CFG_BT_LIGHT_SECURITY_END_ADDR_1_ADDR
#define CONN_INFRA_CFG_BT_LIGHT_SECURITY_END_ADDR_1_R_BT_LIGHT_SECURITY_END_ADDR_1_MASK 0xFFFFFFFF
#define CONN_INFRA_CFG_BT_LIGHT_SECURITY_END_ADDR_1_R_BT_LIGHT_SECURITY_END_ADDR_1_SHFT 0

#define CONN_INFRA_CFG_BT_LIGHT_SECURITY_START_ADDR_2_R_BT_LIGHT_SECURITY_START_ADDR_2_ADDR \
	CONN_INFRA_CFG_BT_LIGHT_SECURITY_START_ADDR_2_ADDR
#define CONN_INFRA_CFG_BT_LIGHT_SECURITY_START_ADDR_2_R_BT_LIGHT_SECURITY_START_ADDR_2_MASK 0xFFFFFFFF
#define CONN_INFRA_CFG_BT_LIGHT_SECURITY_START_ADDR_2_R_BT_LIGHT_SECURITY_START_ADDR_2_SHFT 0

#define CONN_INFRA_CFG_BT_LIGHT_SECURITY_END_ADDR_2_R_BT_LIGHT_SECURITY_END_ADDR_2_ADDR \
	CONN_INFRA_CFG_BT_LIGHT_SECURITY_END_ADDR_2_ADDR
#define CONN_INFRA_CFG_BT_LIGHT_SECURITY_END_ADDR_2_R_BT_LIGHT_SECURITY_END_ADDR_2_MASK 0xFFFFFFFF
#define CONN_INFRA_CFG_BT_LIGHT_SECURITY_END_ADDR_2_R_BT_LIGHT_SECURITY_END_ADDR_2_SHFT 0

#define CONN_INFRA_CFG_BGF_DUMMY_CR_0_BGF_DUMMY_0_ADDR         CONN_INFRA_CFG_BGF_DUMMY_CR_0_ADDR
#define CONN_INFRA_CFG_BGF_DUMMY_CR_0_BGF_DUMMY_0_MASK         0xFFFFFFFF
#define CONN_INFRA_CFG_BGF_DUMMY_CR_0_BGF_DUMMY_0_SHFT         0

#define CONN_INFRA_CFG_BGF_DUMMY_CR_1_BGF_DUMMY_1_ADDR         CONN_INFRA_CFG_BGF_DUMMY_CR_1_ADDR
#define CONN_INFRA_CFG_BGF_DUMMY_CR_1_BGF_DUMMY_1_MASK         0xFFFFFFFF
#define CONN_INFRA_CFG_BGF_DUMMY_CR_1_BGF_DUMMY_1_SHFT         0

#define CONN_INFRA_CFG_BGF_DUMMY_CR_2_BGF_DUMMY_2_ADDR         CONN_INFRA_CFG_BGF_DUMMY_CR_2_ADDR
#define CONN_INFRA_CFG_BGF_DUMMY_CR_2_BGF_DUMMY_2_MASK         0xFFFFFFFF
#define CONN_INFRA_CFG_BGF_DUMMY_CR_2_BGF_DUMMY_2_SHFT         0

#define CONN_INFRA_CFG_BGF_DUMMY_CR_3_BGF_DUMMY_3_ADDR         CONN_INFRA_CFG_BGF_DUMMY_CR_3_ADDR
#define CONN_INFRA_CFG_BGF_DUMMY_CR_3_BGF_DUMMY_3_MASK         0xFFFFFFFF
#define CONN_INFRA_CFG_BGF_DUMMY_CR_3_BGF_DUMMY_3_SHFT         0

#define CONN_INFRA_CFG_WF_DUMMY_CR_0_WF_DUMMY_0_ADDR           CONN_INFRA_CFG_WF_DUMMY_CR_0_ADDR
#define CONN_INFRA_CFG_WF_DUMMY_CR_0_WF_DUMMY_0_MASK           0xFFFFFFFF
#define CONN_INFRA_CFG_WF_DUMMY_CR_0_WF_DUMMY_0_SHFT           0

#define CONN_INFRA_CFG_WF_DUMMY_CR_1_WF_DUMMY_1_ADDR           CONN_INFRA_CFG_WF_DUMMY_CR_1_ADDR
#define CONN_INFRA_CFG_WF_DUMMY_CR_1_WF_DUMMY_1_MASK           0xFFFFFFFF
#define CONN_INFRA_CFG_WF_DUMMY_CR_1_WF_DUMMY_1_SHFT           0

#define CONN_INFRA_CFG_WF_DUMMY_CR_2_WF_DUMMY_2_ADDR           CONN_INFRA_CFG_WF_DUMMY_CR_2_ADDR
#define CONN_INFRA_CFG_WF_DUMMY_CR_2_WF_DUMMY_2_MASK           0xFFFFFFFF
#define CONN_INFRA_CFG_WF_DUMMY_CR_2_WF_DUMMY_2_SHFT           0

#define CONN_INFRA_CFG_WF_DUMMY_CR_3_WF_DUMMY_3_ADDR           CONN_INFRA_CFG_WF_DUMMY_CR_3_ADDR
#define CONN_INFRA_CFG_WF_DUMMY_CR_3_WF_DUMMY_3_MASK           0xFFFFFFFF
#define CONN_INFRA_CFG_WF_DUMMY_CR_3_WF_DUMMY_3_SHFT           0

#define CONN_INFRA_CFG_HOST_CSR_IRQ_EN_CONN_BGF_CR_HOST_CLR_FW_OWN_IRQ_EN_ADDR CONN_INFRA_CFG_HOST_CSR_IRQ_EN_ADDR
#define CONN_INFRA_CFG_HOST_CSR_IRQ_EN_CONN_BGF_CR_HOST_CLR_FW_OWN_IRQ_EN_MASK 0x00000080
#define CONN_INFRA_CFG_HOST_CSR_IRQ_EN_CONN_BGF_CR_HOST_CLR_FW_OWN_IRQ_EN_SHFT 7
#define CONN_INFRA_CFG_HOST_CSR_IRQ_EN_CONN_BGF_CR_HOST_SET_FW_OWN_IRQ_EN_ADDR CONN_INFRA_CFG_HOST_CSR_IRQ_EN_ADDR
#define CONN_INFRA_CFG_HOST_CSR_IRQ_EN_CONN_BGF_CR_HOST_SET_FW_OWN_IRQ_EN_MASK 0x00000040
#define CONN_INFRA_CFG_HOST_CSR_IRQ_EN_CONN_BGF_CR_HOST_SET_FW_OWN_IRQ_EN_SHFT 6
#define CONN_INFRA_CFG_HOST_CSR_IRQ_EN_CONN_CR_MD_CLR_FW_OWN_IRQ_EN_ADDR CONN_INFRA_CFG_HOST_CSR_IRQ_EN_ADDR
#define CONN_INFRA_CFG_HOST_CSR_IRQ_EN_CONN_CR_MD_CLR_FW_OWN_IRQ_EN_MASK 0x00000020
#define CONN_INFRA_CFG_HOST_CSR_IRQ_EN_CONN_CR_MD_CLR_FW_OWN_IRQ_EN_SHFT 5
#define CONN_INFRA_CFG_HOST_CSR_IRQ_EN_CONN_CR_MD_SET_FW_OWN_IRQ_EN_ADDR CONN_INFRA_CFG_HOST_CSR_IRQ_EN_ADDR
#define CONN_INFRA_CFG_HOST_CSR_IRQ_EN_CONN_CR_MD_SET_FW_OWN_IRQ_EN_MASK 0x00000010
#define CONN_INFRA_CFG_HOST_CSR_IRQ_EN_CONN_CR_MD_SET_FW_OWN_IRQ_EN_SHFT 4
#define CONN_INFRA_CFG_HOST_CSR_IRQ_EN_CONN_WF_B1_CR_HOST_CLR_FW_OWN_IRQ_EN_ADDR CONN_INFRA_CFG_HOST_CSR_IRQ_EN_ADDR
#define CONN_INFRA_CFG_HOST_CSR_IRQ_EN_CONN_WF_B1_CR_HOST_CLR_FW_OWN_IRQ_EN_MASK 0x00000008
#define CONN_INFRA_CFG_HOST_CSR_IRQ_EN_CONN_WF_B1_CR_HOST_CLR_FW_OWN_IRQ_EN_SHFT 3
#define CONN_INFRA_CFG_HOST_CSR_IRQ_EN_CONN_WF_B1_CR_HOST_SET_FW_OWN_IRQ_EN_ADDR CONN_INFRA_CFG_HOST_CSR_IRQ_EN_ADDR
#define CONN_INFRA_CFG_HOST_CSR_IRQ_EN_CONN_WF_B1_CR_HOST_SET_FW_OWN_IRQ_EN_MASK 0x00000004
#define CONN_INFRA_CFG_HOST_CSR_IRQ_EN_CONN_WF_B1_CR_HOST_SET_FW_OWN_IRQ_EN_SHFT 2
#define CONN_INFRA_CFG_HOST_CSR_IRQ_EN_CONN_WF_B0_CR_HOST_CLR_FW_OWN_IRQ_EN_ADDR CONN_INFRA_CFG_HOST_CSR_IRQ_EN_ADDR
#define CONN_INFRA_CFG_HOST_CSR_IRQ_EN_CONN_WF_B0_CR_HOST_CLR_FW_OWN_IRQ_EN_MASK 0x00000002
#define CONN_INFRA_CFG_HOST_CSR_IRQ_EN_CONN_WF_B0_CR_HOST_CLR_FW_OWN_IRQ_EN_SHFT 1
#define CONN_INFRA_CFG_HOST_CSR_IRQ_EN_CONN_WF_B0_CR_HOST_SET_FW_OWN_IRQ_EN_ADDR CONN_INFRA_CFG_HOST_CSR_IRQ_EN_ADDR
#define CONN_INFRA_CFG_HOST_CSR_IRQ_EN_CONN_WF_B0_CR_HOST_SET_FW_OWN_IRQ_EN_MASK 0x00000001
#define CONN_INFRA_CFG_HOST_CSR_IRQ_EN_CONN_WF_B0_CR_HOST_SET_FW_OWN_IRQ_EN_SHFT 0

#define CONN_INFRA_CFG_CSR_WF_B0_ON_IRQ_STATUS_CONN_WF_B0_HOST_CLR_FW_OWN_STS_ADDR \
	CONN_INFRA_CFG_CSR_WF_B0_ON_IRQ_STATUS_ADDR
#define CONN_INFRA_CFG_CSR_WF_B0_ON_IRQ_STATUS_CONN_WF_B0_HOST_CLR_FW_OWN_STS_MASK 0x00000002
#define CONN_INFRA_CFG_CSR_WF_B0_ON_IRQ_STATUS_CONN_WF_B0_HOST_CLR_FW_OWN_STS_SHFT 1
#define CONN_INFRA_CFG_CSR_WF_B0_ON_IRQ_STATUS_CONN_WF_B0_HOST_SET_FW_OWN_STS_ADDR \
	CONN_INFRA_CFG_CSR_WF_B0_ON_IRQ_STATUS_ADDR
#define CONN_INFRA_CFG_CSR_WF_B0_ON_IRQ_STATUS_CONN_WF_B0_HOST_SET_FW_OWN_STS_MASK 0x00000001
#define CONN_INFRA_CFG_CSR_WF_B0_ON_IRQ_STATUS_CONN_WF_B0_HOST_SET_FW_OWN_STS_SHFT 0

#define CONN_INFRA_CFG_CSR_WF_B0_ON_HOST_CSR_MISC_CONN_WF_B0_HOST_LPCR_FW_OWN_ADDR \
	CONN_INFRA_CFG_CSR_WF_B0_ON_HOST_CSR_MISC_ADDR
#define CONN_INFRA_CFG_CSR_WF_B0_ON_HOST_CSR_MISC_CONN_WF_B0_HOST_LPCR_FW_OWN_MASK 0x00000001
#define CONN_INFRA_CFG_CSR_WF_B0_ON_HOST_CSR_MISC_CONN_WF_B0_HOST_LPCR_FW_OWN_SHFT 0

#define CONN_INFRA_CFG_CSR_WF_B1_ON_IRQ_STATUS_CONN_WF_B1_HOST_CLR_FW_OWN_STS_ADDR \
	CONN_INFRA_CFG_CSR_WF_B1_ON_IRQ_STATUS_ADDR
#define CONN_INFRA_CFG_CSR_WF_B1_ON_IRQ_STATUS_CONN_WF_B1_HOST_CLR_FW_OWN_STS_MASK 0x00000002
#define CONN_INFRA_CFG_CSR_WF_B1_ON_IRQ_STATUS_CONN_WF_B1_HOST_CLR_FW_OWN_STS_SHFT 1
#define CONN_INFRA_CFG_CSR_WF_B1_ON_IRQ_STATUS_CONN_WF_B1_HOST_SET_FW_OWN_STS_ADDR \
	CONN_INFRA_CFG_CSR_WF_B1_ON_IRQ_STATUS_ADDR
#define CONN_INFRA_CFG_CSR_WF_B1_ON_IRQ_STATUS_CONN_WF_B1_HOST_SET_FW_OWN_STS_MASK 0x00000001
#define CONN_INFRA_CFG_CSR_WF_B1_ON_IRQ_STATUS_CONN_WF_B1_HOST_SET_FW_OWN_STS_SHFT 0

#define CONN_INFRA_CFG_CSR_WF_B1_ON_HOST_CSR_MISC_CONN_WF_B1_HOST_LPCR_FW_OWN_ADDR \
	CONN_INFRA_CFG_CSR_WF_B1_ON_HOST_CSR_MISC_ADDR
#define CONN_INFRA_CFG_CSR_WF_B1_ON_HOST_CSR_MISC_CONN_WF_B1_HOST_LPCR_FW_OWN_MASK 0x00000001
#define CONN_INFRA_CFG_CSR_WF_B1_ON_HOST_CSR_MISC_CONN_WF_B1_HOST_LPCR_FW_OWN_SHFT 0

#define CONN_INFRA_CFG_CSR_MD_ON_IRQ_STATUS_CONN_MD_HOST_CLR_FW_OWN_STS_ADDR CONN_INFRA_CFG_CSR_MD_ON_IRQ_STATUS_ADDR
#define CONN_INFRA_CFG_CSR_MD_ON_IRQ_STATUS_CONN_MD_HOST_CLR_FW_OWN_STS_MASK 0x00000002
#define CONN_INFRA_CFG_CSR_MD_ON_IRQ_STATUS_CONN_MD_HOST_CLR_FW_OWN_STS_SHFT 1
#define CONN_INFRA_CFG_CSR_MD_ON_IRQ_STATUS_CONN_MD_HOST_SET_FW_OWN_STS_ADDR CONN_INFRA_CFG_CSR_MD_ON_IRQ_STATUS_ADDR
#define CONN_INFRA_CFG_CSR_MD_ON_IRQ_STATUS_CONN_MD_HOST_SET_FW_OWN_STS_MASK 0x00000001
#define CONN_INFRA_CFG_CSR_MD_ON_IRQ_STATUS_CONN_MD_HOST_SET_FW_OWN_STS_SHFT 0

#define CONN_INFRA_CFG_CSR_MD_ON_HOST_CSR_MISC_CONN_MD_HOST_LPCR_FW_OWN_ADDR \
	CONN_INFRA_CFG_CSR_MD_ON_HOST_CSR_MISC_ADDR
#define CONN_INFRA_CFG_CSR_MD_ON_HOST_CSR_MISC_CONN_MD_HOST_LPCR_FW_OWN_MASK 0x00000001
#define CONN_INFRA_CFG_CSR_MD_ON_HOST_CSR_MISC_CONN_MD_HOST_LPCR_FW_OWN_SHFT 0

#define CONN_INFRA_CFG_CSR_BGF_ON_IRQ_STATUS_CONN_BGF_HOST_CLR_FW_OWN_STS_ADDR \
	CONN_INFRA_CFG_CSR_BGF_ON_IRQ_STATUS_ADDR
#define CONN_INFRA_CFG_CSR_BGF_ON_IRQ_STATUS_CONN_BGF_HOST_CLR_FW_OWN_STS_MASK 0x00000002
#define CONN_INFRA_CFG_CSR_BGF_ON_IRQ_STATUS_CONN_BGF_HOST_CLR_FW_OWN_STS_SHFT 1
#define CONN_INFRA_CFG_CSR_BGF_ON_IRQ_STATUS_CONN_BGF_HOST_SET_FW_OWN_STS_ADDR \
	CONN_INFRA_CFG_CSR_BGF_ON_IRQ_STATUS_ADDR
#define CONN_INFRA_CFG_CSR_BGF_ON_IRQ_STATUS_CONN_BGF_HOST_SET_FW_OWN_STS_MASK 0x00000001
#define CONN_INFRA_CFG_CSR_BGF_ON_IRQ_STATUS_CONN_BGF_HOST_SET_FW_OWN_STS_SHFT 0

#define CONN_INFRA_CFG_CSR_BGF_ON_HOST_CSR_MISC_CONN_BGF_HOST_LPCR_FW_OWN_ADDR \
	CONN_INFRA_CFG_CSR_BGF_ON_HOST_CSR_MISC_ADDR
#define CONN_INFRA_CFG_CSR_BGF_ON_HOST_CSR_MISC_CONN_BGF_HOST_LPCR_FW_OWN_MASK 0x00000001
#define CONN_INFRA_CFG_CSR_BGF_ON_HOST_CSR_MISC_CONN_BGF_HOST_LPCR_FW_OWN_SHFT 0

#define CONN_INFRA_CFG_CSR_GPS_ON_IRQ_STATUS_CONN_GPS_HOST_CLR_FW_OWN_STS_ADDR \
	CONN_INFRA_CFG_CSR_GPS_ON_IRQ_STATUS_ADDR
#define CONN_INFRA_CFG_CSR_GPS_ON_IRQ_STATUS_CONN_GPS_HOST_CLR_FW_OWN_STS_MASK 0x00000002
#define CONN_INFRA_CFG_CSR_GPS_ON_IRQ_STATUS_CONN_GPS_HOST_CLR_FW_OWN_STS_SHFT 1
#define CONN_INFRA_CFG_CSR_GPS_ON_IRQ_STATUS_CONN_GPS_HOST_SET_FW_OWN_STS_ADDR \
	CONN_INFRA_CFG_CSR_GPS_ON_IRQ_STATUS_ADDR
#define CONN_INFRA_CFG_CSR_GPS_ON_IRQ_STATUS_CONN_GPS_HOST_SET_FW_OWN_STS_MASK 0x00000001
#define CONN_INFRA_CFG_CSR_GPS_ON_IRQ_STATUS_CONN_GPS_HOST_SET_FW_OWN_STS_SHFT 0

#define CONN_INFRA_CFG_CSR_GPS_ON_HOST_CSR_MISC_CONN_GPS_HOST_LPCR_FW_OWN_ADDR \
	CONN_INFRA_CFG_CSR_GPS_ON_HOST_CSR_MISC_ADDR
#define CONN_INFRA_CFG_CSR_GPS_ON_HOST_CSR_MISC_CONN_GPS_HOST_LPCR_FW_OWN_MASK 0x00000001
#define CONN_INFRA_CFG_CSR_GPS_ON_HOST_CSR_MISC_CONN_GPS_HOST_LPCR_FW_OWN_SHFT 0

#define CONN_INFRA_CFG_CSR_BGF_ON_FW_OWN_IRQ_CSR_BGF_ON_FW_OWN_IRQ_ADDR CONN_INFRA_CFG_CSR_BGF_ON_FW_OWN_IRQ_ADDR
#define CONN_INFRA_CFG_CSR_BGF_ON_FW_OWN_IRQ_CSR_BGF_ON_FW_OWN_IRQ_MASK 0x00000001
#define CONN_INFRA_CFG_CSR_BGF_ON_FW_OWN_IRQ_CSR_BGF_ON_FW_OWN_IRQ_SHFT 0

#define CONN_INFRA_CFG_CSR_INFRA_BUS_IDLE_DEBOUNCE_CR_CONN_INFRA_BUS_IDLE_DEBOUNCE_CR_ADDR \
	CONN_INFRA_CFG_CSR_INFRA_BUS_IDLE_DEBOUNCE_CR_ADDR
#define CONN_INFRA_CFG_CSR_INFRA_BUS_IDLE_DEBOUNCE_CR_CONN_INFRA_BUS_IDLE_DEBOUNCE_CR_MASK 0x0000001F
#define CONN_INFRA_CFG_CSR_INFRA_BUS_IDLE_DEBOUNCE_CR_CONN_INFRA_BUS_IDLE_DEBOUNCE_CR_SHFT 0

#define CONN_INFRA_CFG_CSR_INFRA_BUS_IDLE_EN_CONN2HOST_FREQ_BRIDGE_IDLE_EN_ADDR \
	CONN_INFRA_CFG_CSR_INFRA_BUS_IDLE_EN_ADDR
#define CONN_INFRA_CFG_CSR_INFRA_BUS_IDLE_EN_CONN2HOST_FREQ_BRIDGE_IDLE_EN_MASK 0x00000200
#define CONN_INFRA_CFG_CSR_INFRA_BUS_IDLE_EN_CONN2HOST_FREQ_BRIDGE_IDLE_EN_SHFT 9
#define CONN_INFRA_CFG_CSR_INFRA_BUS_IDLE_EN_HOST2CONN_FREQ_BRIDGE_IDLE_EN_ADDR \
	CONN_INFRA_CFG_CSR_INFRA_BUS_IDLE_EN_ADDR
#define CONN_INFRA_CFG_CSR_INFRA_BUS_IDLE_EN_HOST2CONN_FREQ_BRIDGE_IDLE_EN_MASK 0x00000100
#define CONN_INFRA_CFG_CSR_INFRA_BUS_IDLE_EN_HOST2CONN_FREQ_BRIDGE_IDLE_EN_SHFT 8
#define CONN_INFRA_CFG_CSR_INFRA_BUS_IDLE_EN_CONN_BGF_SLAVE_SLICE_IDLE_EN_ADDR \
	CONN_INFRA_CFG_CSR_INFRA_BUS_IDLE_EN_ADDR
#define CONN_INFRA_CFG_CSR_INFRA_BUS_IDLE_EN_CONN_BGF_SLAVE_SLICE_IDLE_EN_MASK 0x00000080
#define CONN_INFRA_CFG_CSR_INFRA_BUS_IDLE_EN_CONN_BGF_SLAVE_SLICE_IDLE_EN_SHFT 7
#define CONN_INFRA_CFG_CSR_INFRA_BUS_IDLE_EN_CONN_BGF_MASTER_SLICE_IDLE_EN_ADDR \
	CONN_INFRA_CFG_CSR_INFRA_BUS_IDLE_EN_ADDR
#define CONN_INFRA_CFG_CSR_INFRA_BUS_IDLE_EN_CONN_BGF_MASTER_SLICE_IDLE_EN_MASK 0x00000040
#define CONN_INFRA_CFG_CSR_INFRA_BUS_IDLE_EN_CONN_BGF_MASTER_SLICE_IDLE_EN_SHFT 6
#define CONN_INFRA_CFG_CSR_INFRA_BUS_IDLE_EN_CONN_BGF_SLAVE_FREQ_BRIDGE_IDLE_EN_ADDR \
	CONN_INFRA_CFG_CSR_INFRA_BUS_IDLE_EN_ADDR
#define CONN_INFRA_CFG_CSR_INFRA_BUS_IDLE_EN_CONN_BGF_SLAVE_FREQ_BRIDGE_IDLE_EN_MASK 0x00000020
#define CONN_INFRA_CFG_CSR_INFRA_BUS_IDLE_EN_CONN_BGF_SLAVE_FREQ_BRIDGE_IDLE_EN_SHFT 5
#define CONN_INFRA_CFG_CSR_INFRA_BUS_IDLE_EN_CONN_BGF_RBIST_FREQ_BRIDGE_IDLE_EN_ADDR \
	CONN_INFRA_CFG_CSR_INFRA_BUS_IDLE_EN_ADDR
#define CONN_INFRA_CFG_CSR_INFRA_BUS_IDLE_EN_CONN_BGF_RBIST_FREQ_BRIDGE_IDLE_EN_MASK 0x00000010
#define CONN_INFRA_CFG_CSR_INFRA_BUS_IDLE_EN_CONN_BGF_RBIST_FREQ_BRIDGE_IDLE_EN_SHFT 4
#define CONN_INFRA_CFG_CSR_INFRA_BUS_IDLE_EN_CONN_BGF_M_FREQ_BRIDGE_IDLE_EN_ADDR \
	CONN_INFRA_CFG_CSR_INFRA_BUS_IDLE_EN_ADDR
#define CONN_INFRA_CFG_CSR_INFRA_BUS_IDLE_EN_CONN_BGF_M_FREQ_BRIDGE_IDLE_EN_MASK 0x00000008
#define CONN_INFRA_CFG_CSR_INFRA_BUS_IDLE_EN_CONN_BGF_M_FREQ_BRIDGE_IDLE_EN_SHFT 3
#define CONN_INFRA_CFG_CSR_INFRA_BUS_IDLE_EN_CONN_WF_SLAVE_FREQ_BRIDGE_IDLE_EN_ADDR \
	CONN_INFRA_CFG_CSR_INFRA_BUS_IDLE_EN_ADDR
#define CONN_INFRA_CFG_CSR_INFRA_BUS_IDLE_EN_CONN_WF_SLAVE_FREQ_BRIDGE_IDLE_EN_MASK 0x00000004
#define CONN_INFRA_CFG_CSR_INFRA_BUS_IDLE_EN_CONN_WF_SLAVE_FREQ_BRIDGE_IDLE_EN_SHFT 2
#define CONN_INFRA_CFG_CSR_INFRA_BUS_IDLE_EN_CONN_WF_RBIST_FREQ_BRIDGE_IDLE_EN_ADDR \
	CONN_INFRA_CFG_CSR_INFRA_BUS_IDLE_EN_ADDR
#define CONN_INFRA_CFG_CSR_INFRA_BUS_IDLE_EN_CONN_WF_RBIST_FREQ_BRIDGE_IDLE_EN_MASK 0x00000002
#define CONN_INFRA_CFG_CSR_INFRA_BUS_IDLE_EN_CONN_WF_RBIST_FREQ_BRIDGE_IDLE_EN_SHFT 1
#define CONN_INFRA_CFG_CSR_INFRA_BUS_IDLE_EN_CONN_WF_MASTER_FREQ_BRIDGE_IDLE_EN_ADDR \
	CONN_INFRA_CFG_CSR_INFRA_BUS_IDLE_EN_ADDR
#define CONN_INFRA_CFG_CSR_INFRA_BUS_IDLE_EN_CONN_WF_MASTER_FREQ_BRIDGE_IDLE_EN_MASK 0x00000001
#define CONN_INFRA_CFG_CSR_INFRA_BUS_IDLE_EN_CONN_WF_MASTER_FREQ_BRIDGE_IDLE_EN_SHFT 0

#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_0_R_CONN_INFRA_SYSRAM_SRAMROM_RAM_DELSEL_ADDR \
	CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_0_ADDR
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_0_R_CONN_INFRA_SYSRAM_SRAMROM_RAM_DELSEL_MASK 0xFFFF0000
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_0_R_CONN_INFRA_SYSRAM_SRAMROM_RAM_DELSEL_SHFT 16
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_0_R_CONN_INFRA_SYSRAM_SRAMROM_RAM_MBIST_BACKGROUND_ADDR \
	CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_0_ADDR
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_0_R_CONN_INFRA_SYSRAM_SRAMROM_RAM_MBIST_BACKGROUND_MASK 0x0000FFFF
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_0_R_CONN_INFRA_SYSRAM_SRAMROM_RAM_MBIST_BACKGROUND_SHFT 0

#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_1_R_CONN_INFRA_SYSRAM_SRAMROM_RAM_MBIST_DONE_ADDR \
	CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_1_ADDR
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_1_R_CONN_INFRA_SYSRAM_SRAMROM_RAM_MBIST_DONE_MASK 0x00200000
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_1_R_CONN_INFRA_SYSRAM_SRAMROM_RAM_MBIST_DONE_SHFT 21
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_1_R_CONN_INFRA_SYSRAM_SRAMROM_RAM_MBIST_FAIL_ADDR \
	CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_1_ADDR
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_1_R_CONN_INFRA_SYSRAM_SRAMROM_RAM_MBIST_FAIL_MASK 0x001FE000
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_1_R_CONN_INFRA_SYSRAM_SRAMROM_RAM_MBIST_FAIL_SHFT 13
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_1_R_CONN_INFRA_SYSRAM_SRAMROM_RAM_MBIST_HOLDB_ADDR \
	CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_1_ADDR
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_1_R_CONN_INFRA_SYSRAM_SRAMROM_RAM_MBIST_HOLDB_MASK 0x00001000
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_1_R_CONN_INFRA_SYSRAM_SRAMROM_RAM_MBIST_HOLDB_SHFT 12
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_1_R_CONN_INFRA_SYSRAM_SRAMROM_RAM_MBIST_DEBUG_ADDR \
	CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_1_ADDR
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_1_R_CONN_INFRA_SYSRAM_SRAMROM_RAM_MBIST_DEBUG_MASK 0x00000800
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_1_R_CONN_INFRA_SYSRAM_SRAMROM_RAM_MBIST_DEBUG_SHFT 11
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_1_R_CONN_INFRA_SYSRAM_SRAMROM_RAM_MBIST_SLEEP_TEST_ADDR \
	CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_1_ADDR
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_1_R_CONN_INFRA_SYSRAM_SRAMROM_RAM_MBIST_SLEEP_TEST_MASK 0x00000400
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_1_R_CONN_INFRA_SYSRAM_SRAMROM_RAM_MBIST_SLEEP_TEST_SHFT 10
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_1_R_CONN_INFRA_SYSRAM_SRAMROM_RAM_MBIST_SLEEP_INV_ADDR \
	CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_1_ADDR
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_1_R_CONN_INFRA_SYSRAM_SRAMROM_RAM_MBIST_SLEEP_INV_MASK 0x00000200
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_1_R_CONN_INFRA_SYSRAM_SRAMROM_RAM_MBIST_SLEEP_INV_SHFT 9
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_1_R_CONN_INFRA_SYSRAM_SRAMROM_RAM_MBIST_SLEEP_R_ADDR \
	CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_1_ADDR
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_1_R_CONN_INFRA_SYSRAM_SRAMROM_RAM_MBIST_SLEEP_R_MASK 0x00000100
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_1_R_CONN_INFRA_SYSRAM_SRAMROM_RAM_MBIST_SLEEP_R_SHFT 8
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_1_R_CONN_INFRA_SYSRAM_SRAMROM_RAM_MBIST_SLEEP_W_ADDR \
	CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_1_ADDR
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_1_R_CONN_INFRA_SYSRAM_SRAMROM_RAM_MBIST_SLEEP_W_MASK 0x00000080
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_1_R_CONN_INFRA_SYSRAM_SRAMROM_RAM_MBIST_SLEEP_W_SHFT 7
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_1_R_CONN_INFRA_SYSRAM_SRAMROM_RAM_MBIST_MODE_ADDR \
	CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_1_ADDR
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_1_R_CONN_INFRA_SYSRAM_SRAMROM_RAM_MBIST_MODE_MASK 0x00000040
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_1_R_CONN_INFRA_SYSRAM_SRAMROM_RAM_MBIST_MODE_SHFT 6
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_1_R_CONN_INFRA_SYSRAM_MBIST_BSEL_ADDR \
	CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_1_ADDR
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_1_R_CONN_INFRA_SYSRAM_MBIST_BSEL_MASK 0x0000003C
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_1_R_CONN_INFRA_SYSRAM_MBIST_BSEL_SHFT 2
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_1_R_CONN_INFRA_SYSRAM_MBIST_USE_DEFAULT_DELSEL_ADDR \
	CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_1_ADDR
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_1_R_CONN_INFRA_SYSRAM_MBIST_USE_DEFAULT_DELSEL_MASK 0x00000002
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_1_R_CONN_INFRA_SYSRAM_MBIST_USE_DEFAULT_DELSEL_SHFT 1
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_1_R_CONN_INFRA_SYSRAM_CG_DISABLE_ADDR \
	CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_1_ADDR
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_1_R_CONN_INFRA_SYSRAM_CG_DISABLE_MASK 0x00000001
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_1_R_CONN_INFRA_SYSRAM_CG_DISABLE_SHFT 0

#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_2_R_CONN_INFRA_SYSRAM_AWT_0_ADDR \
	CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_2_ADDR
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_2_R_CONN_INFRA_SYSRAM_AWT_0_MASK 0x08000000
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_2_R_CONN_INFRA_SYSRAM_AWT_0_SHFT 27
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_2_R_CONN_INFRA_SYSRAM_AWT_1_ADDR \
	CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_2_ADDR
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_2_R_CONN_INFRA_SYSRAM_AWT_1_MASK 0x04000000
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_2_R_CONN_INFRA_SYSRAM_AWT_1_SHFT 26
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_2_R_CONN_INFRA_SYSRAM_AWT_2_ADDR \
	CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_2_ADDR
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_2_R_CONN_INFRA_SYSRAM_AWT_2_MASK 0x02000000
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_2_R_CONN_INFRA_SYSRAM_AWT_2_SHFT 25
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_2_R_CONN_INFRA_SYSRAM_AWT_3_ADDR \
	CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_2_ADDR
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_2_R_CONN_INFRA_SYSRAM_AWT_3_MASK 0x01000000
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_2_R_CONN_INFRA_SYSRAM_AWT_3_SHFT 24
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_2_R_CONN_INFRA_SYSRAM_AWT_4_ADDR \
	CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_2_ADDR
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_2_R_CONN_INFRA_SYSRAM_AWT_4_MASK 0x00800000
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_2_R_CONN_INFRA_SYSRAM_AWT_4_SHFT 23
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_2_R_CONN_INFRA_SYSRAM_AWT_5_ADDR \
	CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_2_ADDR
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_2_R_CONN_INFRA_SYSRAM_AWT_5_MASK 0x00400000
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_2_R_CONN_INFRA_SYSRAM_AWT_5_SHFT 22
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_2_R_CONN_INFRA_SYSRAM_AWT_6_ADDR \
	CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_2_ADDR
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_2_R_CONN_INFRA_SYSRAM_AWT_6_MASK 0x00200000
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_2_R_CONN_INFRA_SYSRAM_AWT_6_SHFT 21
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_2_R_CONN_INFRA_SYSRAM_AWT_7_ADDR \
	CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_2_ADDR
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_2_R_CONN_INFRA_SYSRAM_AWT_7_MASK 0x00100000
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_2_R_CONN_INFRA_SYSRAM_AWT_7_SHFT 20
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_2_R_CONN_INFRA_SYSRAM_SRAMROM_EAM_DELSEL_UMS_ADDR \
	CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_2_ADDR
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_2_R_CONN_INFRA_SYSRAM_SRAMROM_EAM_DELSEL_UMS_MASK 0x000FFFFF
#define CONN_INFRA_CFG_CONN_INFRA_SYSRAM_CTRL_2_R_CONN_INFRA_SYSRAM_SRAMROM_EAM_DELSEL_UMS_SHFT 0

#define CONN_INFRA_CFG_GALS_WFDMA_SLP_EN_R_GALS_MASTER_WFDMA0_SLP_EN_ADDR CONN_INFRA_CFG_GALS_WFDMA_SLP_EN_ADDR
#define CONN_INFRA_CFG_GALS_WFDMA_SLP_EN_R_GALS_MASTER_WFDMA0_SLP_EN_MASK 0x00000001
#define CONN_INFRA_CFG_GALS_WFDMA_SLP_EN_R_GALS_MASTER_WFDMA0_SLP_EN_SHFT 0
#define CONN_INFRA_CFG_GALS_WFDMA_SLP_EN_RO_GALS_MASTER_WFDMA0_SLP_RDY_ADDR CONN_INFRA_CFG_GALS_WFDMA_SLP_EN_ADDR
#define CONN_INFRA_CFG_GALS_WFDMA_SLP_EN_RO_GALS_MASTER_WFDMA0_SLP_RDY_MASK 0x00000002
#define CONN_INFRA_CFG_GALS_WFDMA_SLP_EN_RO_GALS_MASTER_WFDMA0_SLP_RDY_SHFT 1
#define CONN_INFRA_CFG_GALS_WFDMA_SLP_EN_R_GALS_SLAVE_WFDMA0_SLP_EN_ADDR CONN_INFRA_CFG_GALS_WFDMA_SLP_EN_ADDR
#define CONN_INFRA_CFG_GALS_WFDMA_SLP_EN_R_GALS_SLAVE_WFDMA0_SLP_EN_MASK 0x00000004
#define CONN_INFRA_CFG_GALS_WFDMA_SLP_EN_R_GALS_SLAVE_WFDMA0_SLP_EN_SHFT 2
#define CONN_INFRA_CFG_GALS_WFDMA_SLP_EN_RO_GALS_SLAVE_WFDMA0_SLP_RDY_ADDR CONN_INFRA_CFG_GALS_WFDMA_SLP_EN_ADDR
#define CONN_INFRA_CFG_GALS_WFDMA_SLP_EN_RO_GALS_SLAVE_WFDMA0_SLP_RDY_MASK 0x00000008
#define CONN_INFRA_CFG_GALS_WFDMA_SLP_EN_RO_GALS_SLAVE_WFDMA0_SLP_RDY_SHFT 3
#define CONN_INFRA_CFG_GALS_WFDMA_SLP_EN_R_GALS_MASTER_WFDMA1_SLP_EN_ADDR CONN_INFRA_CFG_GALS_WFDMA_SLP_EN_ADDR
#define CONN_INFRA_CFG_GALS_WFDMA_SLP_EN_R_GALS_MASTER_WFDMA1_SLP_EN_MASK 0x00000010
#define CONN_INFRA_CFG_GALS_WFDMA_SLP_EN_R_GALS_MASTER_WFDMA1_SLP_EN_SHFT 4
#define CONN_INFRA_CFG_GALS_WFDMA_SLP_EN_RO_GALS_MASTER_WFDMA1_SLP_RDY_ADDR CONN_INFRA_CFG_GALS_WFDMA_SLP_EN_ADDR
#define CONN_INFRA_CFG_GALS_WFDMA_SLP_EN_RO_GALS_MASTER_WFDMA1_SLP_RDY_MASK 0x00000020
#define CONN_INFRA_CFG_GALS_WFDMA_SLP_EN_RO_GALS_MASTER_WFDMA1_SLP_RDY_SHFT 5
#define CONN_INFRA_CFG_GALS_WFDMA_SLP_EN_R_GALS_SLAVE_WFDMA1_SLP_EN_ADDR CONN_INFRA_CFG_GALS_WFDMA_SLP_EN_ADDR
#define CONN_INFRA_CFG_GALS_WFDMA_SLP_EN_R_GALS_SLAVE_WFDMA1_SLP_EN_MASK 0x00000040
#define CONN_INFRA_CFG_GALS_WFDMA_SLP_EN_R_GALS_SLAVE_WFDMA1_SLP_EN_SHFT 6
#define CONN_INFRA_CFG_GALS_WFDMA_SLP_EN_RO_GALS_SLAVE_WFDMA1_SLP_RDY_ADDR CONN_INFRA_CFG_GALS_WFDMA_SLP_EN_ADDR
#define CONN_INFRA_CFG_GALS_WFDMA_SLP_EN_RO_GALS_SLAVE_WFDMA1_SLP_RDY_MASK 0x00000080
#define CONN_INFRA_CFG_GALS_WFDMA_SLP_EN_RO_GALS_SLAVE_WFDMA1_SLP_RDY_SHFT 7

#define CONN_INFRA_CFG_GALS_CONN2BT_SLP_CTRL_R_CONN2BT_SLP_PROT_TX_EN_ADDR CONN_INFRA_CFG_GALS_CONN2BT_SLP_CTRL_ADDR
#define CONN_INFRA_CFG_GALS_CONN2BT_SLP_CTRL_R_CONN2BT_SLP_PROT_TX_EN_MASK 0x00000001
#define CONN_INFRA_CFG_GALS_CONN2BT_SLP_CTRL_R_CONN2BT_SLP_PROT_TX_EN_SHFT 0
#define CONN_INFRA_CFG_GALS_CONN2BT_SLP_CTRL_R_CONN2BT_SLP_PROT_TX_DIS_ADDR CONN_INFRA_CFG_GALS_CONN2BT_SLP_CTRL_ADDR
#define CONN_INFRA_CFG_GALS_CONN2BT_SLP_CTRL_R_CONN2BT_SLP_PROT_TX_DIS_MASK 0x00000002
#define CONN_INFRA_CFG_GALS_CONN2BT_SLP_CTRL_R_CONN2BT_SLP_PROT_TX_DIS_SHFT 1
#define CONN_INFRA_CFG_GALS_CONN2BT_SLP_CTRL_R_CONN2BT_SLP_PROT_TX_HW_EN_ADDR CONN_INFRA_CFG_GALS_CONN2BT_SLP_CTRL_ADDR
#define CONN_INFRA_CFG_GALS_CONN2BT_SLP_CTRL_R_CONN2BT_SLP_PROT_TX_HW_EN_MASK 0x00000004
#define CONN_INFRA_CFG_GALS_CONN2BT_SLP_CTRL_R_CONN2BT_SLP_PROT_TX_HW_EN_SHFT 2
#define CONN_INFRA_CFG_GALS_CONN2BT_SLP_CTRL_R_CONN2BT_SLP_PROT_TX_RDY_ADDR CONN_INFRA_CFG_GALS_CONN2BT_SLP_CTRL_ADDR
#define CONN_INFRA_CFG_GALS_CONN2BT_SLP_CTRL_R_CONN2BT_SLP_PROT_TX_RDY_MASK 0x00000008
#define CONN_INFRA_CFG_GALS_CONN2BT_SLP_CTRL_R_CONN2BT_SLP_PROT_TX_RDY_SHFT 3
#define CONN_INFRA_CFG_GALS_CONN2BT_SLP_CTRL_R_CONN2BT_SLP_PROT_RX_EN_ADDR CONN_INFRA_CFG_GALS_CONN2BT_SLP_CTRL_ADDR
#define CONN_INFRA_CFG_GALS_CONN2BT_SLP_CTRL_R_CONN2BT_SLP_PROT_RX_EN_MASK 0x00000010
#define CONN_INFRA_CFG_GALS_CONN2BT_SLP_CTRL_R_CONN2BT_SLP_PROT_RX_EN_SHFT 4
#define CONN_INFRA_CFG_GALS_CONN2BT_SLP_CTRL_R_CONN2BT_SLP_PROT_RX_DIS_ADDR CONN_INFRA_CFG_GALS_CONN2BT_SLP_CTRL_ADDR
#define CONN_INFRA_CFG_GALS_CONN2BT_SLP_CTRL_R_CONN2BT_SLP_PROT_RX_DIS_MASK 0x00000020
#define CONN_INFRA_CFG_GALS_CONN2BT_SLP_CTRL_R_CONN2BT_SLP_PROT_RX_DIS_SHFT 5
#define CONN_INFRA_CFG_GALS_CONN2BT_SLP_CTRL_R_CONN2BT_SLP_PROT_RX_RDY_ADDR CONN_INFRA_CFG_GALS_CONN2BT_SLP_CTRL_ADDR
#define CONN_INFRA_CFG_GALS_CONN2BT_SLP_CTRL_R_CONN2BT_SLP_PROT_RX_RDY_MASK 0x00000080
#define CONN_INFRA_CFG_GALS_CONN2BT_SLP_CTRL_R_CONN2BT_SLP_PROT_RX_RDY_SHFT 7

#define CONN_INFRA_CFG_GALS_BT2CONN_SLP_CTRL_R_BT2CONN_SLP_PROT_TX_EN_ADDR CONN_INFRA_CFG_GALS_BT2CONN_SLP_CTRL_ADDR
#define CONN_INFRA_CFG_GALS_BT2CONN_SLP_CTRL_R_BT2CONN_SLP_PROT_TX_EN_MASK 0x00000001
#define CONN_INFRA_CFG_GALS_BT2CONN_SLP_CTRL_R_BT2CONN_SLP_PROT_TX_EN_SHFT 0
#define CONN_INFRA_CFG_GALS_BT2CONN_SLP_CTRL_R_BT2CONN_SLP_PROT_TX_DIS_ADDR CONN_INFRA_CFG_GALS_BT2CONN_SLP_CTRL_ADDR
#define CONN_INFRA_CFG_GALS_BT2CONN_SLP_CTRL_R_BT2CONN_SLP_PROT_TX_DIS_MASK 0x00000002
#define CONN_INFRA_CFG_GALS_BT2CONN_SLP_CTRL_R_BT2CONN_SLP_PROT_TX_DIS_SHFT 1
#define CONN_INFRA_CFG_GALS_BT2CONN_SLP_CTRL_R_BT2CONN_SLP_PROT_TX_RDY_ADDR CONN_INFRA_CFG_GALS_BT2CONN_SLP_CTRL_ADDR
#define CONN_INFRA_CFG_GALS_BT2CONN_SLP_CTRL_R_BT2CONN_SLP_PROT_TX_RDY_MASK 0x00000008
#define CONN_INFRA_CFG_GALS_BT2CONN_SLP_CTRL_R_BT2CONN_SLP_PROT_TX_RDY_SHFT 3
#define CONN_INFRA_CFG_GALS_BT2CONN_SLP_CTRL_R_BT2CONN_SLP_PROT_RX_EN_ADDR CONN_INFRA_CFG_GALS_BT2CONN_SLP_CTRL_ADDR
#define CONN_INFRA_CFG_GALS_BT2CONN_SLP_CTRL_R_BT2CONN_SLP_PROT_RX_EN_MASK 0x00000010
#define CONN_INFRA_CFG_GALS_BT2CONN_SLP_CTRL_R_BT2CONN_SLP_PROT_RX_EN_SHFT 4
#define CONN_INFRA_CFG_GALS_BT2CONN_SLP_CTRL_R_BT2CONN_SLP_PROT_RX_DIS_ADDR CONN_INFRA_CFG_GALS_BT2CONN_SLP_CTRL_ADDR
#define CONN_INFRA_CFG_GALS_BT2CONN_SLP_CTRL_R_BT2CONN_SLP_PROT_RX_DIS_MASK 0x00000020
#define CONN_INFRA_CFG_GALS_BT2CONN_SLP_CTRL_R_BT2CONN_SLP_PROT_RX_DIS_SHFT 5
#define CONN_INFRA_CFG_GALS_BT2CONN_SLP_CTRL_R_BT2CONN_SLP_PROT_TX_HW_EN_ADDR CONN_INFRA_CFG_GALS_BT2CONN_SLP_CTRL_ADDR
#define CONN_INFRA_CFG_GALS_BT2CONN_SLP_CTRL_R_BT2CONN_SLP_PROT_TX_HW_EN_MASK 0x00000040
#define CONN_INFRA_CFG_GALS_BT2CONN_SLP_CTRL_R_BT2CONN_SLP_PROT_TX_HW_EN_SHFT 6
#define CONN_INFRA_CFG_GALS_BT2CONN_SLP_CTRL_R_BT2CONN_SLP_PROT_RX_RDY_ADDR CONN_INFRA_CFG_GALS_BT2CONN_SLP_CTRL_ADDR
#define CONN_INFRA_CFG_GALS_BT2CONN_SLP_CTRL_R_BT2CONN_SLP_PROT_RX_RDY_MASK 0x00000080
#define CONN_INFRA_CFG_GALS_BT2CONN_SLP_CTRL_R_BT2CONN_SLP_PROT_RX_RDY_SHFT 7

#define CONN_INFRA_CFG_GALS_CONN2GPS_SLP_CTRL_R_CONN2GPS_SLP_PROT_TX_EN_ADDR CONN_INFRA_CFG_GALS_CONN2GPS_SLP_CTRL_ADDR
#define CONN_INFRA_CFG_GALS_CONN2GPS_SLP_CTRL_R_CONN2GPS_SLP_PROT_TX_EN_MASK 0x00000001
#define CONN_INFRA_CFG_GALS_CONN2GPS_SLP_CTRL_R_CONN2GPS_SLP_PROT_TX_EN_SHFT 0
#define CONN_INFRA_CFG_GALS_CONN2GPS_SLP_CTRL_R_CONN2GPS_SLP_PROT_TX_DIS_ADDR \
	CONN_INFRA_CFG_GALS_CONN2GPS_SLP_CTRL_ADDR
#define CONN_INFRA_CFG_GALS_CONN2GPS_SLP_CTRL_R_CONN2GPS_SLP_PROT_TX_DIS_MASK 0x00000002
#define CONN_INFRA_CFG_GALS_CONN2GPS_SLP_CTRL_R_CONN2GPS_SLP_PROT_TX_DIS_SHFT 1
#define CONN_INFRA_CFG_GALS_CONN2GPS_SLP_CTRL_R_CONN2GPS_SLP_PROT_TX_HW_EN_ADDR \
	CONN_INFRA_CFG_GALS_CONN2GPS_SLP_CTRL_ADDR
#define CONN_INFRA_CFG_GALS_CONN2GPS_SLP_CTRL_R_CONN2GPS_SLP_PROT_TX_HW_EN_MASK 0x00000004
#define CONN_INFRA_CFG_GALS_CONN2GPS_SLP_CTRL_R_CONN2GPS_SLP_PROT_TX_HW_EN_SHFT 2
#define CONN_INFRA_CFG_GALS_CONN2GPS_SLP_CTRL_R_CONN2GPS_SLP_PROT_TX_RDY_ADDR \
	CONN_INFRA_CFG_GALS_CONN2GPS_SLP_CTRL_ADDR
#define CONN_INFRA_CFG_GALS_CONN2GPS_SLP_CTRL_R_CONN2GPS_SLP_PROT_TX_RDY_MASK 0x00000008
#define CONN_INFRA_CFG_GALS_CONN2GPS_SLP_CTRL_R_CONN2GPS_SLP_PROT_TX_RDY_SHFT 3
#define CONN_INFRA_CFG_GALS_CONN2GPS_SLP_CTRL_R_CONN2GPS_SLP_PROT_RX_EN_ADDR CONN_INFRA_CFG_GALS_CONN2GPS_SLP_CTRL_ADDR
#define CONN_INFRA_CFG_GALS_CONN2GPS_SLP_CTRL_R_CONN2GPS_SLP_PROT_RX_EN_MASK 0x00000010
#define CONN_INFRA_CFG_GALS_CONN2GPS_SLP_CTRL_R_CONN2GPS_SLP_PROT_RX_EN_SHFT 4
#define CONN_INFRA_CFG_GALS_CONN2GPS_SLP_CTRL_R_CONN2GPS_SLP_PROT_RX_DIS_ADDR \
	CONN_INFRA_CFG_GALS_CONN2GPS_SLP_CTRL_ADDR
#define CONN_INFRA_CFG_GALS_CONN2GPS_SLP_CTRL_R_CONN2GPS_SLP_PROT_RX_DIS_MASK 0x00000020
#define CONN_INFRA_CFG_GALS_CONN2GPS_SLP_CTRL_R_CONN2GPS_SLP_PROT_RX_DIS_SHFT 5
#define CONN_INFRA_CFG_GALS_CONN2GPS_SLP_CTRL_R_CONN2GPS_SLP_PROT_RX_RDY_ADDR \
	CONN_INFRA_CFG_GALS_CONN2GPS_SLP_CTRL_ADDR
#define CONN_INFRA_CFG_GALS_CONN2GPS_SLP_CTRL_R_CONN2GPS_SLP_PROT_RX_RDY_MASK 0x00000080
#define CONN_INFRA_CFG_GALS_CONN2GPS_SLP_CTRL_R_CONN2GPS_SLP_PROT_RX_RDY_SHFT 7

#define CONN_INFRA_CFG_GALS_GPS2CONN_SLP_CTRL_R_GPS2CONN_SLP_PROT_TX_EN_ADDR CONN_INFRA_CFG_GALS_GPS2CONN_SLP_CTRL_ADDR
#define CONN_INFRA_CFG_GALS_GPS2CONN_SLP_CTRL_R_GPS2CONN_SLP_PROT_TX_EN_MASK 0x00000001
#define CONN_INFRA_CFG_GALS_GPS2CONN_SLP_CTRL_R_GPS2CONN_SLP_PROT_TX_EN_SHFT 0
#define CONN_INFRA_CFG_GALS_GPS2CONN_SLP_CTRL_R_GPS2CONN_SLP_PROT_TX_DIS_ADDR \
	CONN_INFRA_CFG_GALS_GPS2CONN_SLP_CTRL_ADDR
#define CONN_INFRA_CFG_GALS_GPS2CONN_SLP_CTRL_R_GPS2CONN_SLP_PROT_TX_DIS_MASK 0x00000002
#define CONN_INFRA_CFG_GALS_GPS2CONN_SLP_CTRL_R_GPS2CONN_SLP_PROT_TX_DIS_SHFT 1
#define CONN_INFRA_CFG_GALS_GPS2CONN_SLP_CTRL_R_GPS2CONN_SLP_PROT_TX_RDY_ADDR \
	CONN_INFRA_CFG_GALS_GPS2CONN_SLP_CTRL_ADDR
#define CONN_INFRA_CFG_GALS_GPS2CONN_SLP_CTRL_R_GPS2CONN_SLP_PROT_TX_RDY_MASK 0x00000008
#define CONN_INFRA_CFG_GALS_GPS2CONN_SLP_CTRL_R_GPS2CONN_SLP_PROT_TX_RDY_SHFT 3
#define CONN_INFRA_CFG_GALS_GPS2CONN_SLP_CTRL_R_GPS2CONN_SLP_PROT_RX_EN_ADDR CONN_INFRA_CFG_GALS_GPS2CONN_SLP_CTRL_ADDR
#define CONN_INFRA_CFG_GALS_GPS2CONN_SLP_CTRL_R_GPS2CONN_SLP_PROT_RX_EN_MASK 0x00000010
#define CONN_INFRA_CFG_GALS_GPS2CONN_SLP_CTRL_R_GPS2CONN_SLP_PROT_RX_EN_SHFT 4
#define CONN_INFRA_CFG_GALS_GPS2CONN_SLP_CTRL_R_GPS2CONN_SLP_PROT_RX_DIS_ADDR \
	CONN_INFRA_CFG_GALS_GPS2CONN_SLP_CTRL_ADDR
#define CONN_INFRA_CFG_GALS_GPS2CONN_SLP_CTRL_R_GPS2CONN_SLP_PROT_RX_DIS_MASK 0x00000020
#define CONN_INFRA_CFG_GALS_GPS2CONN_SLP_CTRL_R_GPS2CONN_SLP_PROT_RX_DIS_SHFT 5
#define CONN_INFRA_CFG_GALS_GPS2CONN_SLP_CTRL_R_GPS2CONN_SLP_PROT_TX_HW_EN_ADDR \
	CONN_INFRA_CFG_GALS_GPS2CONN_SLP_CTRL_ADDR
#define CONN_INFRA_CFG_GALS_GPS2CONN_SLP_CTRL_R_GPS2CONN_SLP_PROT_TX_HW_EN_MASK 0x00000040
#define CONN_INFRA_CFG_GALS_GPS2CONN_SLP_CTRL_R_GPS2CONN_SLP_PROT_TX_HW_EN_SHFT 6
#define CONN_INFRA_CFG_GALS_GPS2CONN_SLP_CTRL_R_GPS2CONN_SLP_PROT_RX_RDY_ADDR \
	CONN_INFRA_CFG_GALS_GPS2CONN_SLP_CTRL_ADDR
#define CONN_INFRA_CFG_GALS_GPS2CONN_SLP_CTRL_R_GPS2CONN_SLP_PROT_RX_RDY_MASK 0x00000080
#define CONN_INFRA_CFG_GALS_GPS2CONN_SLP_CTRL_R_GPS2CONN_SLP_PROT_RX_RDY_SHFT 7

#define CONN_INFRA_CFG_CONN_INFRA_WF_SLP_CTRL_R_CONN_WF_SLP_SW_EN_ADDR CONN_INFRA_CFG_CONN_INFRA_WF_SLP_CTRL_ADDR
#define CONN_INFRA_CFG_CONN_INFRA_WF_SLP_CTRL_R_CONN_WF_SLP_SW_EN_MASK 0x00000001
#define CONN_INFRA_CFG_CONN_INFRA_WF_SLP_CTRL_R_CONN_WF_SLP_SW_EN_SHFT 0
#define CONN_INFRA_CFG_CONN_INFRA_WF_SLP_CTRL_R_CONN_WF_SLP_SW_DIS_ADDR CONN_INFRA_CFG_CONN_INFRA_WF_SLP_CTRL_ADDR
#define CONN_INFRA_CFG_CONN_INFRA_WF_SLP_CTRL_R_CONN_WF_SLP_SW_DIS_MASK 0x00000002
#define CONN_INFRA_CFG_CONN_INFRA_WF_SLP_CTRL_R_CONN_WF_SLP_SW_DIS_SHFT 1
#define CONN_INFRA_CFG_CONN_INFRA_WF_SLP_CTRL_R_CONN_WF_SLP_HW_EN_ADDR CONN_INFRA_CFG_CONN_INFRA_WF_SLP_CTRL_ADDR
#define CONN_INFRA_CFG_CONN_INFRA_WF_SLP_CTRL_R_CONN_WF_SLP_HW_EN_MASK 0x00000004
#define CONN_INFRA_CFG_CONN_INFRA_WF_SLP_CTRL_R_CONN_WF_SLP_HW_EN_SHFT 2
#define CONN_INFRA_CFG_CONN_INFRA_WF_SLP_CTRL_R_CONN_WF_SLP_RDY_ADDR CONN_INFRA_CFG_CONN_INFRA_WF_SLP_CTRL_ADDR
#define CONN_INFRA_CFG_CONN_INFRA_WF_SLP_CTRL_R_CONN_WF_SLP_RDY_MASK 0x00000008
#define CONN_INFRA_CFG_CONN_INFRA_WF_SLP_CTRL_R_CONN_WF_SLP_RDY_SHFT 3

#define CONN_INFRA_CFG_CONN_INFRA_WFDMA_SLP_CTRL_R_CONN_WFDMA_SLP_SW_EN_ADDR \
	CONN_INFRA_CFG_CONN_INFRA_WFDMA_SLP_CTRL_ADDR
#define CONN_INFRA_CFG_CONN_INFRA_WFDMA_SLP_CTRL_R_CONN_WFDMA_SLP_SW_EN_MASK 0x00000001
#define CONN_INFRA_CFG_CONN_INFRA_WFDMA_SLP_CTRL_R_CONN_WFDMA_SLP_SW_EN_SHFT 0
#define CONN_INFRA_CFG_CONN_INFRA_WFDMA_SLP_CTRL_R_CONN_WFDMA_SLP_SW_DIS_ADDR \
	CONN_INFRA_CFG_CONN_INFRA_WFDMA_SLP_CTRL_ADDR
#define CONN_INFRA_CFG_CONN_INFRA_WFDMA_SLP_CTRL_R_CONN_WFDMA_SLP_SW_DIS_MASK 0x00000002
#define CONN_INFRA_CFG_CONN_INFRA_WFDMA_SLP_CTRL_R_CONN_WFDMA_SLP_SW_DIS_SHFT 1
#define CONN_INFRA_CFG_CONN_INFRA_WFDMA_SLP_CTRL_R_CONN_WFDMA_SLP_HW_EN_ADDR \
	CONN_INFRA_CFG_CONN_INFRA_WFDMA_SLP_CTRL_ADDR
#define CONN_INFRA_CFG_CONN_INFRA_WFDMA_SLP_CTRL_R_CONN_WFDMA_SLP_HW_EN_MASK 0x00000004
#define CONN_INFRA_CFG_CONN_INFRA_WFDMA_SLP_CTRL_R_CONN_WFDMA_SLP_HW_EN_SHFT 2
#define CONN_INFRA_CFG_CONN_INFRA_WFDMA_SLP_CTRL_R_CONN_WFDMA_SLP_RDY_ADDR \
	CONN_INFRA_CFG_CONN_INFRA_WFDMA_SLP_CTRL_ADDR
#define CONN_INFRA_CFG_CONN_INFRA_WFDMA_SLP_CTRL_R_CONN_WFDMA_SLP_RDY_MASK 0x00000008
#define CONN_INFRA_CFG_CONN_INFRA_WFDMA_SLP_CTRL_R_CONN_WFDMA_SLP_RDY_SHFT 3

#define CONN_INFRA_CFG_CONN_INFRA_ON_BUS_SLP_CTRL_CONN_INFRA_ON_BUS_SLP_PROT_SW_EN_ADDR \
	CONN_INFRA_CFG_CONN_INFRA_ON_BUS_SLP_CTRL_ADDR
#define CONN_INFRA_CFG_CONN_INFRA_ON_BUS_SLP_CTRL_CONN_INFRA_ON_BUS_SLP_PROT_SW_EN_MASK 0x00000001
#define CONN_INFRA_CFG_CONN_INFRA_ON_BUS_SLP_CTRL_CONN_INFRA_ON_BUS_SLP_PROT_SW_EN_SHFT 0
#define CONN_INFRA_CFG_CONN_INFRA_ON_BUS_SLP_CTRL_CONN_INFRA_ON_BUS_SLP_PROT_SW_DIS_ADDR \
	CONN_INFRA_CFG_CONN_INFRA_ON_BUS_SLP_CTRL_ADDR
#define CONN_INFRA_CFG_CONN_INFRA_ON_BUS_SLP_CTRL_CONN_INFRA_ON_BUS_SLP_PROT_SW_DIS_MASK 0x00000002
#define CONN_INFRA_CFG_CONN_INFRA_ON_BUS_SLP_CTRL_CONN_INFRA_ON_BUS_SLP_PROT_SW_DIS_SHFT 1
#define CONN_INFRA_CFG_CONN_INFRA_ON_BUS_SLP_CTRL_CONN_INFRA_ON_BUS_SLP_PROT_HW_EN_ADDR \
	CONN_INFRA_CFG_CONN_INFRA_ON_BUS_SLP_CTRL_ADDR
#define CONN_INFRA_CFG_CONN_INFRA_ON_BUS_SLP_CTRL_CONN_INFRA_ON_BUS_SLP_PROT_HW_EN_MASK 0x00000004
#define CONN_INFRA_CFG_CONN_INFRA_ON_BUS_SLP_CTRL_CONN_INFRA_ON_BUS_SLP_PROT_HW_EN_SHFT 2
#define CONN_INFRA_CFG_CONN_INFRA_ON_BUS_SLP_CTRL_CONN_INFRA_ON_BUS_SLP_PROT_RDY_ADDR \
	CONN_INFRA_CFG_CONN_INFRA_ON_BUS_SLP_CTRL_ADDR
#define CONN_INFRA_CFG_CONN_INFRA_ON_BUS_SLP_CTRL_CONN_INFRA_ON_BUS_SLP_PROT_RDY_MASK 0x00000008
#define CONN_INFRA_CFG_CONN_INFRA_ON_BUS_SLP_CTRL_CONN_INFRA_ON_BUS_SLP_PROT_RDY_SHFT 3

#define CONN_INFRA_CFG_CONN_INFRA_OFF_BUS_SLP_CTRL_CONN_INFRA_OFF_BUS_SLP_PROT_SW_EN_ADDR \
	CONN_INFRA_CFG_CONN_INFRA_OFF_BUS_SLP_CTRL_ADDR
#define CONN_INFRA_CFG_CONN_INFRA_OFF_BUS_SLP_CTRL_CONN_INFRA_OFF_BUS_SLP_PROT_SW_EN_MASK 0x00000001
#define CONN_INFRA_CFG_CONN_INFRA_OFF_BUS_SLP_CTRL_CONN_INFRA_OFF_BUS_SLP_PROT_SW_EN_SHFT 0
#define CONN_INFRA_CFG_CONN_INFRA_OFF_BUS_SLP_CTRL_CONN_INFRA_OFF_BUS_SLP_PROT_SW_DIS_ADDR \
	CONN_INFRA_CFG_CONN_INFRA_OFF_BUS_SLP_CTRL_ADDR
#define CONN_INFRA_CFG_CONN_INFRA_OFF_BUS_SLP_CTRL_CONN_INFRA_OFF_BUS_SLP_PROT_SW_DIS_MASK 0x00000002
#define CONN_INFRA_CFG_CONN_INFRA_OFF_BUS_SLP_CTRL_CONN_INFRA_OFF_BUS_SLP_PROT_SW_DIS_SHFT 1
#define CONN_INFRA_CFG_CONN_INFRA_OFF_BUS_SLP_CTRL_CONN_INFRA_OFF_BUS_SLP_PROT_HW_EN_ADDR \
	CONN_INFRA_CFG_CONN_INFRA_OFF_BUS_SLP_CTRL_ADDR
#define CONN_INFRA_CFG_CONN_INFRA_OFF_BUS_SLP_CTRL_CONN_INFRA_OFF_BUS_SLP_PROT_HW_EN_MASK 0x00000004
#define CONN_INFRA_CFG_CONN_INFRA_OFF_BUS_SLP_CTRL_CONN_INFRA_OFF_BUS_SLP_PROT_HW_EN_SHFT 2
#define CONN_INFRA_CFG_CONN_INFRA_OFF_BUS_SLP_CTRL_CONN_INFRA_OFF_BUS_SLP_PROT_RDY_ADDR \
	CONN_INFRA_CFG_CONN_INFRA_OFF_BUS_SLP_CTRL_ADDR
#define CONN_INFRA_CFG_CONN_INFRA_OFF_BUS_SLP_CTRL_CONN_INFRA_OFF_BUS_SLP_PROT_RDY_MASK 0x00000008
#define CONN_INFRA_CFG_CONN_INFRA_OFF_BUS_SLP_CTRL_CONN_INFRA_OFF_BUS_SLP_PROT_RDY_SHFT 3

#define CONN_INFRA_CFG_CONN_INFRA_GALS_CONN2AP_TX_SLP_CTRL_CONN_INFRA_GALS_CONN2AP_TX_SLP_PROT_SW_EN_ADDR \
	CONN_INFRA_CFG_CONN_INFRA_GALS_CONN2AP_TX_SLP_CTRL_ADDR
#define CONN_INFRA_CFG_CONN_INFRA_GALS_CONN2AP_TX_SLP_CTRL_CONN_INFRA_GALS_CONN2AP_TX_SLP_PROT_SW_EN_MASK 0x00000001
#define CONN_INFRA_CFG_CONN_INFRA_GALS_CONN2AP_TX_SLP_CTRL_CONN_INFRA_GALS_CONN2AP_TX_SLP_PROT_SW_EN_SHFT 0
#define CONN_INFRA_CFG_CONN_INFRA_GALS_CONN2AP_TX_SLP_CTRL_CONN_INFRA_GALS_CONN2AP_TX_SLP_PROT_SW_DIS_ADDR \
	CONN_INFRA_CFG_CONN_INFRA_GALS_CONN2AP_TX_SLP_CTRL_ADDR
#define CONN_INFRA_CFG_CONN_INFRA_GALS_CONN2AP_TX_SLP_CTRL_CONN_INFRA_GALS_CONN2AP_TX_SLP_PROT_SW_DIS_MASK 0x00000002
#define CONN_INFRA_CFG_CONN_INFRA_GALS_CONN2AP_TX_SLP_CTRL_CONN_INFRA_GALS_CONN2AP_TX_SLP_PROT_SW_DIS_SHFT 1
#define CONN_INFRA_CFG_CONN_INFRA_GALS_CONN2AP_TX_SLP_CTRL_CONN_INFRA_GALS_CONN2AP_TX_SLP_PROT_HW_EN_ADDR \
	CONN_INFRA_CFG_CONN_INFRA_GALS_CONN2AP_TX_SLP_CTRL_ADDR
#define CONN_INFRA_CFG_CONN_INFRA_GALS_CONN2AP_TX_SLP_CTRL_CONN_INFRA_GALS_CONN2AP_TX_SLP_PROT_HW_EN_MASK 0x00000004
#define CONN_INFRA_CFG_CONN_INFRA_GALS_CONN2AP_TX_SLP_CTRL_CONN_INFRA_GALS_CONN2AP_TX_SLP_PROT_HW_EN_SHFT 2
#define CONN_INFRA_CFG_CONN_INFRA_GALS_CONN2AP_TX_SLP_CTRL_CONN_INFRA_GALS_CONN2AP_TX_SLP_PROT_RDY_ADDR \
	CONN_INFRA_CFG_CONN_INFRA_GALS_CONN2AP_TX_SLP_CTRL_ADDR
#define CONN_INFRA_CFG_CONN_INFRA_GALS_CONN2AP_TX_SLP_CTRL_CONN_INFRA_GALS_CONN2AP_TX_SLP_PROT_RDY_MASK 0x00000008
#define CONN_INFRA_CFG_CONN_INFRA_GALS_CONN2AP_TX_SLP_CTRL_CONN_INFRA_GALS_CONN2AP_TX_SLP_PROT_RDY_SHFT 3

#define CONN_INFRA_CFG_CONN_INFRA_GALS_CONN2AP_RX_SLP_CTRL_CONN_INFRA_GALS_CONN2AP_RX_SLP_PROT_SW_EN_ADDR \
	CONN_INFRA_CFG_CONN_INFRA_GALS_CONN2AP_RX_SLP_CTRL_ADDR
#define CONN_INFRA_CFG_CONN_INFRA_GALS_CONN2AP_RX_SLP_CTRL_CONN_INFRA_GALS_CONN2AP_RX_SLP_PROT_SW_EN_MASK 0x00000001
#define CONN_INFRA_CFG_CONN_INFRA_GALS_CONN2AP_RX_SLP_CTRL_CONN_INFRA_GALS_CONN2AP_RX_SLP_PROT_SW_EN_SHFT 0
#define CONN_INFRA_CFG_CONN_INFRA_GALS_CONN2AP_RX_SLP_CTRL_CONN_INFRA_GALS_CONN2AP_RX_SLP_PROT_SW_DIS_ADDR \
	CONN_INFRA_CFG_CONN_INFRA_GALS_CONN2AP_RX_SLP_CTRL_ADDR
#define CONN_INFRA_CFG_CONN_INFRA_GALS_CONN2AP_RX_SLP_CTRL_CONN_INFRA_GALS_CONN2AP_RX_SLP_PROT_SW_DIS_MASK 0x00000002
#define CONN_INFRA_CFG_CONN_INFRA_GALS_CONN2AP_RX_SLP_CTRL_CONN_INFRA_GALS_CONN2AP_RX_SLP_PROT_SW_DIS_SHFT 1
#define CONN_INFRA_CFG_CONN_INFRA_GALS_CONN2AP_RX_SLP_CTRL_CONN_INFRA_GALS_CONN2AP_RX_SLP_PROT_HW_EN_ADDR \
	CONN_INFRA_CFG_CONN_INFRA_GALS_CONN2AP_RX_SLP_CTRL_ADDR
#define CONN_INFRA_CFG_CONN_INFRA_GALS_CONN2AP_RX_SLP_CTRL_CONN_INFRA_GALS_CONN2AP_RX_SLP_PROT_HW_EN_MASK 0x00000004
#define CONN_INFRA_CFG_CONN_INFRA_GALS_CONN2AP_RX_SLP_CTRL_CONN_INFRA_GALS_CONN2AP_RX_SLP_PROT_HW_EN_SHFT 2
#define CONN_INFRA_CFG_CONN_INFRA_GALS_CONN2AP_RX_SLP_CTRL_CONN_INFRA_GALS_CONN2AP_RX_SLP_PROT_RDY_ADDR \
	CONN_INFRA_CFG_CONN_INFRA_GALS_CONN2AP_RX_SLP_CTRL_ADDR
#define CONN_INFRA_CFG_CONN_INFRA_GALS_CONN2AP_RX_SLP_CTRL_CONN_INFRA_GALS_CONN2AP_RX_SLP_PROT_RDY_MASK 0x00000008
#define CONN_INFRA_CFG_CONN_INFRA_GALS_CONN2AP_RX_SLP_CTRL_CONN_INFRA_GALS_CONN2AP_RX_SLP_PROT_RDY_SHFT 3

#define CONN_INFRA_CFG_CONN_INFRA_GALS_CONN2AP_SLP_CTRL_RST_CONN_INFRA_GALS_CONN2AP_SLP_STATE_RST_ADDR \
	CONN_INFRA_CFG_CONN_INFRA_GALS_CONN2AP_SLP_CTRL_RST_ADDR
#define CONN_INFRA_CFG_CONN_INFRA_GALS_CONN2AP_SLP_CTRL_RST_CONN_INFRA_GALS_CONN2AP_SLP_STATE_RST_MASK 0x00000001
#define CONN_INFRA_CFG_CONN_INFRA_GALS_CONN2AP_SLP_CTRL_RST_CONN_INFRA_GALS_CONN2AP_SLP_STATE_RST_SHFT 0

#define CONN_INFRA_CFG_OSC_CTL_0_XO_BG_STABLE_TIME_ADDR        CONN_INFRA_CFG_OSC_CTL_0_ADDR
#define CONN_INFRA_CFG_OSC_CTL_0_XO_BG_STABLE_TIME_MASK        0x00FF0000
#define CONN_INFRA_CFG_OSC_CTL_0_XO_BG_STABLE_TIME_SHFT        16
#define CONN_INFRA_CFG_OSC_CTL_0_XO_INI_STABLE_TIME_ADDR       CONN_INFRA_CFG_OSC_CTL_0_ADDR
#define CONN_INFRA_CFG_OSC_CTL_0_XO_INI_STABLE_TIME_MASK       0x0000FF00
#define CONN_INFRA_CFG_OSC_CTL_0_XO_INI_STABLE_TIME_SHFT       8
#define CONN_INFRA_CFG_OSC_CTL_0_XO_VCORE_RDY_STABLE_TIME_ADDR CONN_INFRA_CFG_OSC_CTL_0_ADDR
#define CONN_INFRA_CFG_OSC_CTL_0_XO_VCORE_RDY_STABLE_TIME_MASK 0x000000FF
#define CONN_INFRA_CFG_OSC_CTL_0_XO_VCORE_RDY_STABLE_TIME_SHFT 0

#define CONN_INFRA_CFG_OSC_CTL_1_XO_NO_OFF_ADDR                CONN_INFRA_CFG_OSC_CTL_1_ADDR
#define CONN_INFRA_CFG_OSC_CTL_1_XO_NO_OFF_MASK                0x80000000
#define CONN_INFRA_CFG_OSC_CTL_1_XO_NO_OFF_SHFT                31
#define CONN_INFRA_CFG_OSC_CTL_1_ACK_FOR_XO_STATE_MASK_ADDR    CONN_INFRA_CFG_OSC_CTL_1_ADDR
#define CONN_INFRA_CFG_OSC_CTL_1_ACK_FOR_XO_STATE_MASK_MASK    0x00010000
#define CONN_INFRA_CFG_OSC_CTL_1_ACK_FOR_XO_STATE_MASK_SHFT    16
#define CONN_INFRA_CFG_OSC_CTL_1_SW_OSC_RDY_ADDR               CONN_INFRA_CFG_OSC_CTL_1_ADDR
#define CONN_INFRA_CFG_OSC_CTL_1_SW_OSC_RDY_MASK               0x00001000
#define CONN_INFRA_CFG_OSC_CTL_1_SW_OSC_RDY_SHFT               12
#define CONN_INFRA_CFG_OSC_CTL_1_SW_VCORE_RDY_ADDR             CONN_INFRA_CFG_OSC_CTL_1_ADDR
#define CONN_INFRA_CFG_OSC_CTL_1_SW_VCORE_RDY_MASK             0x00000800
#define CONN_INFRA_CFG_OSC_CTL_1_SW_VCORE_RDY_SHFT             11
#define CONN_INFRA_CFG_OSC_CTL_1_SW_EN_XBUF_ADDR               CONN_INFRA_CFG_OSC_CTL_1_ADDR
#define CONN_INFRA_CFG_OSC_CTL_1_SW_EN_XBUF_MASK               0x00000400
#define CONN_INFRA_CFG_OSC_CTL_1_SW_EN_XBUF_SHFT               10
#define CONN_INFRA_CFG_OSC_CTL_1_SW_EN_BG_ADDR                 CONN_INFRA_CFG_OSC_CTL_1_ADDR
#define CONN_INFRA_CFG_OSC_CTL_1_SW_EN_BG_MASK                 0x00000200
#define CONN_INFRA_CFG_OSC_CTL_1_SW_EN_BG_SHFT                 9
#define CONN_INFRA_CFG_OSC_CTL_1_SW_SRCCLKENA_ADDR             CONN_INFRA_CFG_OSC_CTL_1_ADDR
#define CONN_INFRA_CFG_OSC_CTL_1_SW_SRCCLKENA_MASK             0x00000100
#define CONN_INFRA_CFG_OSC_CTL_1_SW_SRCCLKENA_SHFT             8
#define CONN_INFRA_CFG_OSC_CTL_1_SWCTL_OSC_RDY_ADDR            CONN_INFRA_CFG_OSC_CTL_1_ADDR
#define CONN_INFRA_CFG_OSC_CTL_1_SWCTL_OSC_RDY_MASK            0x00000010
#define CONN_INFRA_CFG_OSC_CTL_1_SWCTL_OSC_RDY_SHFT            4
#define CONN_INFRA_CFG_OSC_CTL_1_SWCTL_VCORE_RDY_ADDR          CONN_INFRA_CFG_OSC_CTL_1_ADDR
#define CONN_INFRA_CFG_OSC_CTL_1_SWCTL_VCORE_RDY_MASK          0x00000008
#define CONN_INFRA_CFG_OSC_CTL_1_SWCTL_VCORE_RDY_SHFT          3
#define CONN_INFRA_CFG_OSC_CTL_1_SWCTL_EN_XBUF_ADDR            CONN_INFRA_CFG_OSC_CTL_1_ADDR
#define CONN_INFRA_CFG_OSC_CTL_1_SWCTL_EN_XBUF_MASK            0x00000004
#define CONN_INFRA_CFG_OSC_CTL_1_SWCTL_EN_XBUF_SHFT            2
#define CONN_INFRA_CFG_OSC_CTL_1_SWCTL_EN_BG_ADDR              CONN_INFRA_CFG_OSC_CTL_1_ADDR
#define CONN_INFRA_CFG_OSC_CTL_1_SWCTL_EN_BG_MASK              0x00000002
#define CONN_INFRA_CFG_OSC_CTL_1_SWCTL_EN_BG_SHFT              1
#define CONN_INFRA_CFG_OSC_CTL_1_SWCTL_SRCCLKENA_ADDR          CONN_INFRA_CFG_OSC_CTL_1_ADDR
#define CONN_INFRA_CFG_OSC_CTL_1_SWCTL_SRCCLKENA_MASK          0x00000001
#define CONN_INFRA_CFG_OSC_CTL_1_SWCTL_SRCCLKENA_SHFT          0

#define CONN_INFRA_CFG_OSC_MASK_AP2CONN_OSC_EN_ADDR            CONN_INFRA_CFG_OSC_MASK_ADDR
#define CONN_INFRA_CFG_OSC_MASK_AP2CONN_OSC_EN_MASK            0x00002000
#define CONN_INFRA_CFG_OSC_MASK_AP2CONN_OSC_EN_SHFT            13
#define CONN_INFRA_CFG_OSC_MASK_CONN_THM_OSC_EN_ADDR           CONN_INFRA_CFG_OSC_MASK_ADDR
#define CONN_INFRA_CFG_OSC_MASK_CONN_THM_OSC_EN_MASK           0x00001000
#define CONN_INFRA_CFG_OSC_MASK_CONN_THM_OSC_EN_SHFT           12
#define CONN_INFRA_CFG_OSC_MASK_CONN_PTA_OSC_EN_ADDR           CONN_INFRA_CFG_OSC_MASK_ADDR
#define CONN_INFRA_CFG_OSC_MASK_CONN_PTA_OSC_EN_MASK           0x00000800
#define CONN_INFRA_CFG_OSC_MASK_CONN_PTA_OSC_EN_SHFT           11
#define CONN_INFRA_CFG_OSC_MASK_CONN_INFRA_BUS_OSC_EN_ADDR     CONN_INFRA_CFG_OSC_MASK_ADDR
#define CONN_INFRA_CFG_OSC_MASK_CONN_INFRA_BUS_OSC_EN_MASK     0x00000400
#define CONN_INFRA_CFG_OSC_MASK_CONN_INFRA_BUS_OSC_EN_SHFT     10
#define CONN_INFRA_CFG_OSC_MASK_BGFSYS_OSC_ON_ADDR             CONN_INFRA_CFG_OSC_MASK_ADDR
#define CONN_INFRA_CFG_OSC_MASK_BGFSYS_OSC_ON_MASK             0x00000200
#define CONN_INFRA_CFG_OSC_MASK_BGFSYS_OSC_ON_SHFT             9
#define CONN_INFRA_CFG_OSC_MASK_WFSYS_OSC_ON_ADDR              CONN_INFRA_CFG_OSC_MASK_ADDR
#define CONN_INFRA_CFG_OSC_MASK_WFSYS_OSC_ON_MASK              0x00000100
#define CONN_INFRA_CFG_OSC_MASK_WFSYS_OSC_ON_SHFT              8
#define CONN_INFRA_CFG_OSC_MASK_OSC_EN_MASK_ADDR               CONN_INFRA_CFG_OSC_MASK_ADDR
#define CONN_INFRA_CFG_OSC_MASK_OSC_EN_MASK_MASK               0x0000003F
#define CONN_INFRA_CFG_OSC_MASK_OSC_EN_MASK_SHFT               0

#define CONN_INFRA_CFG_OSC_STATUS_HW_CONNSRCCLKENA_ADDR        CONN_INFRA_CFG_OSC_STATUS_ADDR
#define CONN_INFRA_CFG_OSC_STATUS_HW_CONNSRCCLKENA_MASK        0x00010000
#define CONN_INFRA_CFG_OSC_STATUS_HW_CONNSRCCLKENA_SHFT        16
#define CONN_INFRA_CFG_OSC_STATUS_HW_VCORE_RDY_ADDR            CONN_INFRA_CFG_OSC_STATUS_ADDR
#define CONN_INFRA_CFG_OSC_STATUS_HW_VCORE_RDY_MASK            0x00008000
#define CONN_INFRA_CFG_OSC_STATUS_HW_VCORE_RDY_SHFT            15
#define CONN_INFRA_CFG_OSC_STATUS_HW_DA_WBG_EN_BG_ADDR         CONN_INFRA_CFG_OSC_STATUS_ADDR
#define CONN_INFRA_CFG_OSC_STATUS_HW_DA_WBG_EN_BG_MASK         0x00004000
#define CONN_INFRA_CFG_OSC_STATUS_HW_DA_WBG_EN_BG_SHFT         14
#define CONN_INFRA_CFG_OSC_STATUS_HW_DA_WBG_EN_XBUF_ADDR       CONN_INFRA_CFG_OSC_STATUS_ADDR
#define CONN_INFRA_CFG_OSC_STATUS_HW_DA_WBG_EN_XBUF_MASK       0x00002000
#define CONN_INFRA_CFG_OSC_STATUS_HW_DA_WBG_EN_XBUF_SHFT       13
#define CONN_INFRA_CFG_OSC_STATUS_HW_OSC_RDY_ADDR              CONN_INFRA_CFG_OSC_STATUS_ADDR
#define CONN_INFRA_CFG_OSC_STATUS_HW_OSC_RDY_MASK              0x00001000
#define CONN_INFRA_CFG_OSC_STATUS_HW_OSC_RDY_SHFT              12
#define CONN_INFRA_CFG_OSC_STATUS_XO_EN_ADDR                   CONN_INFRA_CFG_OSC_STATUS_ADDR
#define CONN_INFRA_CFG_OSC_STATUS_XO_EN_MASK                   0x00000800
#define CONN_INFRA_CFG_OSC_STATUS_XO_EN_SHFT                   11
#define CONN_INFRA_CFG_OSC_STATUS_XO_STATE_ADDR                CONN_INFRA_CFG_OSC_STATUS_ADDR
#define CONN_INFRA_CFG_OSC_STATUS_XO_STATE_MASK                0x00000700
#define CONN_INFRA_CFG_OSC_STATUS_XO_STATE_SHFT                8
#define CONN_INFRA_CFG_OSC_STATUS_BUS_WFSYS_CK_SW_RDY_ADDR     CONN_INFRA_CFG_OSC_STATUS_ADDR
#define CONN_INFRA_CFG_OSC_STATUS_BUS_WFSYS_CK_SW_RDY_MASK     0x00000008
#define CONN_INFRA_CFG_OSC_STATUS_BUS_WFSYS_CK_SW_RDY_SHFT     3
#define CONN_INFRA_CFG_OSC_STATUS_BUS_BGFSYS_CK_SW_RDY_ADDR    CONN_INFRA_CFG_OSC_STATUS_ADDR
#define CONN_INFRA_CFG_OSC_STATUS_BUS_BGFSYS_CK_SW_RDY_MASK    0x00000004
#define CONN_INFRA_CFG_OSC_STATUS_BUS_BGFSYS_CK_SW_RDY_SHFT    2
#define CONN_INFRA_CFG_OSC_STATUS_BUS_32K_SW_RDY_ADDR          CONN_INFRA_CFG_OSC_STATUS_ADDR
#define CONN_INFRA_CFG_OSC_STATUS_BUS_32K_SW_RDY_MASK          0x00000002
#define CONN_INFRA_CFG_OSC_STATUS_BUS_32K_SW_RDY_SHFT          1
#define CONN_INFRA_CFG_OSC_STATUS_BUS_OSC_SW_RDY_ADDR          CONN_INFRA_CFG_OSC_STATUS_ADDR
#define CONN_INFRA_CFG_OSC_STATUS_BUS_OSC_SW_RDY_MASK          0x00000001
#define CONN_INFRA_CFG_OSC_STATUS_BUS_OSC_SW_RDY_SHFT          0

#define CONN_INFRA_CFG_PLL_STATUS_BPLL_RDY_ADDR                CONN_INFRA_CFG_PLL_STATUS_ADDR
#define CONN_INFRA_CFG_PLL_STATUS_BPLL_RDY_MASK                0x00000002
#define CONN_INFRA_CFG_PLL_STATUS_BPLL_RDY_SHFT                1
#define CONN_INFRA_CFG_PLL_STATUS_WPLL_RDY_ADDR                CONN_INFRA_CFG_PLL_STATUS_ADDR
#define CONN_INFRA_CFG_PLL_STATUS_WPLL_RDY_MASK                0x00000001
#define CONN_INFRA_CFG_PLL_STATUS_WPLL_RDY_SHFT                0

#define CONN_INFRA_CFG_STRAP_STATUS_CONN_SPEEDUP_OSC_STABLE_MODE_ADDR CONN_INFRA_CFG_STRAP_STATUS_ADDR
#define CONN_INFRA_CFG_STRAP_STATUS_CONN_SPEEDUP_OSC_STABLE_MODE_MASK 0x00040000
#define CONN_INFRA_CFG_STRAP_STATUS_CONN_SPEEDUP_OSC_STABLE_MODE_SHFT 18
#define CONN_INFRA_CFG_STRAP_STATUS_CONN_BYPASS_ROM_MODE_ADDR  CONN_INFRA_CFG_STRAP_STATUS_ADDR
#define CONN_INFRA_CFG_STRAP_STATUS_CONN_BYPASS_ROM_MODE_MASK  0x00020000
#define CONN_INFRA_CFG_STRAP_STATUS_CONN_BYPASS_ROM_MODE_SHFT  17
#define CONN_INFRA_CFG_STRAP_STATUS_CONN_EXTCK_MODE_ADDR       CONN_INFRA_CFG_STRAP_STATUS_ADDR
#define CONN_INFRA_CFG_STRAP_STATUS_CONN_EXTCK_MODE_MASK       0x00010000
#define CONN_INFRA_CFG_STRAP_STATUS_CONN_EXTCK_MODE_SHFT       16
#define CONN_INFRA_CFG_STRAP_STATUS_CONN_FORCE_PWR_ON_MODE_ADDR CONN_INFRA_CFG_STRAP_STATUS_ADDR
#define CONN_INFRA_CFG_STRAP_STATUS_CONN_FORCE_PWR_ON_MODE_MASK 0x00008000
#define CONN_INFRA_CFG_STRAP_STATUS_CONN_FORCE_PWR_ON_MODE_SHFT 15
#define CONN_INFRA_CFG_STRAP_STATUS_CONN_TEST_MODE_ADDR        CONN_INFRA_CFG_STRAP_STATUS_ADDR
#define CONN_INFRA_CFG_STRAP_STATUS_CONN_TEST_MODE_MASK        0x00004000
#define CONN_INFRA_CFG_STRAP_STATUS_CONN_TEST_MODE_SHFT        14
#define CONN_INFRA_CFG_STRAP_STATUS_CONN_SPI2AHB_MODE_ADDR     CONN_INFRA_CFG_STRAP_STATUS_ADDR
#define CONN_INFRA_CFG_STRAP_STATUS_CONN_SPI2AHB_MODE_MASK     0x00002000
#define CONN_INFRA_CFG_STRAP_STATUS_CONN_SPI2AHB_MODE_SHFT     13
#define CONN_INFRA_CFG_STRAP_STATUS_RBIST_MODE_ADDR            CONN_INFRA_CFG_STRAP_STATUS_ADDR
#define CONN_INFRA_CFG_STRAP_STATUS_RBIST_MODE_MASK            0x00001000
#define CONN_INFRA_CFG_STRAP_STATUS_RBIST_MODE_SHFT            12
#define CONN_INFRA_CFG_STRAP_STATUS_BGFSYSSTRAP_MODE_ADDR      CONN_INFRA_CFG_STRAP_STATUS_ADDR
#define CONN_INFRA_CFG_STRAP_STATUS_BGFSYSSTRAP_MODE_MASK      0x00000800
#define CONN_INFRA_CFG_STRAP_STATUS_BGFSYSSTRAP_MODE_SHFT      11
#define CONN_INFRA_CFG_STRAP_STATUS_WFSYSSTRAP_MODE_ADDR       CONN_INFRA_CFG_STRAP_STATUS_ADDR
#define CONN_INFRA_CFG_STRAP_STATUS_WFSYSSTRAP_MODE_MASK       0x00000400
#define CONN_INFRA_CFG_STRAP_STATUS_WFSYSSTRAP_MODE_SHFT       10
#define CONN_INFRA_CFG_STRAP_STATUS_SYSSTRAP_MODE_ADDR         CONN_INFRA_CFG_STRAP_STATUS_ADDR
#define CONN_INFRA_CFG_STRAP_STATUS_SYSSTRAP_MODE_MASK         0x00000200
#define CONN_INFRA_CFG_STRAP_STATUS_SYSSTRAP_MODE_SHFT         9
#define CONN_INFRA_CFG_STRAP_STATUS_OLT_BLT_MODE_ADDR          CONN_INFRA_CFG_STRAP_STATUS_ADDR
#define CONN_INFRA_CFG_STRAP_STATUS_OLT_BLT_MODE_MASK          0x00000100
#define CONN_INFRA_CFG_STRAP_STATUS_OLT_BLT_MODE_SHFT          8
#define CONN_INFRA_CFG_STRAP_STATUS_OSC_IS_52M_ADDR            CONN_INFRA_CFG_STRAP_STATUS_ADDR
#define CONN_INFRA_CFG_STRAP_STATUS_OSC_IS_52M_MASK            0x00000020
#define CONN_INFRA_CFG_STRAP_STATUS_OSC_IS_52M_SHFT            5
#define CONN_INFRA_CFG_STRAP_STATUS_OSC_IS_40M_ADDR            CONN_INFRA_CFG_STRAP_STATUS_ADDR
#define CONN_INFRA_CFG_STRAP_STATUS_OSC_IS_40M_MASK            0x00000010
#define CONN_INFRA_CFG_STRAP_STATUS_OSC_IS_40M_SHFT            4
#define CONN_INFRA_CFG_STRAP_STATUS_OSC_IS_26M_ADDR            CONN_INFRA_CFG_STRAP_STATUS_ADDR
#define CONN_INFRA_CFG_STRAP_STATUS_OSC_IS_26M_MASK            0x00000008
#define CONN_INFRA_CFG_STRAP_STATUS_OSC_IS_26M_SHFT            3
#define CONN_INFRA_CFG_STRAP_STATUS_OSC_IS_25M_ADDR            CONN_INFRA_CFG_STRAP_STATUS_ADDR
#define CONN_INFRA_CFG_STRAP_STATUS_OSC_IS_25M_MASK            0x00000004
#define CONN_INFRA_CFG_STRAP_STATUS_OSC_IS_25M_SHFT            2
#define CONN_INFRA_CFG_STRAP_STATUS_OSC_IS_24M_ADDR            CONN_INFRA_CFG_STRAP_STATUS_ADDR
#define CONN_INFRA_CFG_STRAP_STATUS_OSC_IS_24M_MASK            0x00000002
#define CONN_INFRA_CFG_STRAP_STATUS_OSC_IS_24M_SHFT            1
#define CONN_INFRA_CFG_STRAP_STATUS_OSC_IS_20M_ADDR            CONN_INFRA_CFG_STRAP_STATUS_ADDR
#define CONN_INFRA_CFG_STRAP_STATUS_OSC_IS_20M_MASK            0x00000001
#define CONN_INFRA_CFG_STRAP_STATUS_OSC_IS_20M_SHFT            0

#define CONN_INFRA_CFG_EFUSE_AP2CONN_EFUSE_DATA_ADDR           CONN_INFRA_CFG_EFUSE_ADDR
#define CONN_INFRA_CFG_EFUSE_AP2CONN_EFUSE_DATA_MASK           0x0000FFFF
#define CONN_INFRA_CFG_EFUSE_AP2CONN_EFUSE_DATA_SHFT           0

#define CONN_INFRA_CFG_BOOT_WF_CPU_BOOT_DONE_ADDR              CONN_INFRA_CFG_BOOT_ADDR
#define CONN_INFRA_CFG_BOOT_WF_CPU_BOOT_DONE_MASK              0x80000000
#define CONN_INFRA_CFG_BOOT_WF_CPU_BOOT_DONE_SHFT              31
#define CONN_INFRA_CFG_BOOT_BGF_CPU_BOOT_DONE_ADDR             CONN_INFRA_CFG_BOOT_ADDR
#define CONN_INFRA_CFG_BOOT_BGF_CPU_BOOT_DONE_MASK             0x40000000
#define CONN_INFRA_CFG_BOOT_BGF_CPU_BOOT_DONE_SHFT             30
#define CONN_INFRA_CFG_BOOT_AP2CONN_BOOT_CPU_SEL_ADDR          CONN_INFRA_CFG_BOOT_ADDR
#define CONN_INFRA_CFG_BOOT_AP2CONN_BOOT_CPU_SEL_MASK          0x00000001
#define CONN_INFRA_CFG_BOOT_AP2CONN_BOOT_CPU_SEL_SHFT          0

#define CONN_INFRA_CFG_RC_STATUS_CONN_V_REQ_3_ADDR             CONN_INFRA_CFG_RC_STATUS_ADDR
#define CONN_INFRA_CFG_RC_STATUS_CONN_V_REQ_3_MASK             0x80000000
#define CONN_INFRA_CFG_RC_STATUS_CONN_V_REQ_3_SHFT             31
#define CONN_INFRA_CFG_RC_STATUS_CONN_V_REQ_2_ADDR             CONN_INFRA_CFG_RC_STATUS_ADDR
#define CONN_INFRA_CFG_RC_STATUS_CONN_V_REQ_2_MASK             0x40000000
#define CONN_INFRA_CFG_RC_STATUS_CONN_V_REQ_2_SHFT             30
#define CONN_INFRA_CFG_RC_STATUS_CONN_V_REQ_1_ADDR             CONN_INFRA_CFG_RC_STATUS_ADDR
#define CONN_INFRA_CFG_RC_STATUS_CONN_V_REQ_1_MASK             0x20000000
#define CONN_INFRA_CFG_RC_STATUS_CONN_V_REQ_1_SHFT             29
#define CONN_INFRA_CFG_RC_STATUS_CONN_V_REQ_0_ADDR             CONN_INFRA_CFG_RC_STATUS_ADDR
#define CONN_INFRA_CFG_RC_STATUS_CONN_V_REQ_0_MASK             0x10000000
#define CONN_INFRA_CFG_RC_STATUS_CONN_V_REQ_0_SHFT             28
#define CONN_INFRA_CFG_RC_STATUS_CONN_INFRA_VCORE_RDY_ADDR     CONN_INFRA_CFG_RC_STATUS_ADDR
#define CONN_INFRA_CFG_RC_STATUS_CONN_INFRA_VCORE_RDY_MASK     0x08000000
#define CONN_INFRA_CFG_RC_STATUS_CONN_INFRA_VCORE_RDY_SHFT     27
#define CONN_INFRA_CFG_RC_STATUS_CONN_INFRA_OSC_ON_ACK_ADDR    CONN_INFRA_CFG_RC_STATUS_ADDR
#define CONN_INFRA_CFG_RC_STATUS_CONN_INFRA_OSC_ON_ACK_MASK    0x04000000
#define CONN_INFRA_CFG_RC_STATUS_CONN_INFRA_OSC_ON_ACK_SHFT    26
#define CONN_INFRA_CFG_RC_STATUS_WFSYS_VCORE_RDY_ADDR          CONN_INFRA_CFG_RC_STATUS_ADDR
#define CONN_INFRA_CFG_RC_STATUS_WFSYS_VCORE_RDY_MASK          0x02000000
#define CONN_INFRA_CFG_RC_STATUS_WFSYS_VCORE_RDY_SHFT          25
#define CONN_INFRA_CFG_RC_STATUS_WFSYS_OSC_ON_ACK_ADDR         CONN_INFRA_CFG_RC_STATUS_ADDR
#define CONN_INFRA_CFG_RC_STATUS_WFSYS_OSC_ON_ACK_MASK         0x01000000
#define CONN_INFRA_CFG_RC_STATUS_WFSYS_OSC_ON_ACK_SHFT         24
#define CONN_INFRA_CFG_RC_STATUS_BTSYS_VCORE_RDY_ADDR          CONN_INFRA_CFG_RC_STATUS_ADDR
#define CONN_INFRA_CFG_RC_STATUS_BTSYS_VCORE_RDY_MASK          0x00800000
#define CONN_INFRA_CFG_RC_STATUS_BTSYS_VCORE_RDY_SHFT          23
#define CONN_INFRA_CFG_RC_STATUS_BTSYS_OSC_ON_ACK_ADDR         CONN_INFRA_CFG_RC_STATUS_ADDR
#define CONN_INFRA_CFG_RC_STATUS_BTSYS_OSC_ON_ACK_MASK         0x00400000
#define CONN_INFRA_CFG_RC_STATUS_BTSYS_OSC_ON_ACK_SHFT         22
#define CONN_INFRA_CFG_RC_STATUS_GPSSYS_VCORE_RDY_ADDR         CONN_INFRA_CFG_RC_STATUS_ADDR
#define CONN_INFRA_CFG_RC_STATUS_GPSSYS_VCORE_RDY_MASK         0x00200000
#define CONN_INFRA_CFG_RC_STATUS_GPSSYS_VCORE_RDY_SHFT         21
#define CONN_INFRA_CFG_RC_STATUS_GPSSYS_OSC_ON_ACK_ADDR        CONN_INFRA_CFG_RC_STATUS_ADDR
#define CONN_INFRA_CFG_RC_STATUS_GPSSYS_OSC_ON_ACK_MASK        0x00100000
#define CONN_INFRA_CFG_RC_STATUS_GPSSYS_OSC_ON_ACK_SHFT        20
#define CONN_INFRA_CFG_RC_STATUS_CONN_SRCCLKENA_3_FPM_ACK_ADDR CONN_INFRA_CFG_RC_STATUS_ADDR
#define CONN_INFRA_CFG_RC_STATUS_CONN_SRCCLKENA_3_FPM_ACK_MASK 0x00080000
#define CONN_INFRA_CFG_RC_STATUS_CONN_SRCCLKENA_3_FPM_ACK_SHFT 19
#define CONN_INFRA_CFG_RC_STATUS_CONN_SRCCLKENA_3_BBLPM_ACK_ADDR CONN_INFRA_CFG_RC_STATUS_ADDR
#define CONN_INFRA_CFG_RC_STATUS_CONN_SRCCLKENA_3_BBLPM_ACK_MASK 0x00040000
#define CONN_INFRA_CFG_RC_STATUS_CONN_SRCCLKENA_3_BBLPM_ACK_SHFT 18
#define CONN_INFRA_CFG_RC_STATUS_CONN_SRCCLKENA_3_FPM_ADDR     CONN_INFRA_CFG_RC_STATUS_ADDR
#define CONN_INFRA_CFG_RC_STATUS_CONN_SRCCLKENA_3_FPM_MASK     0x00020000
#define CONN_INFRA_CFG_RC_STATUS_CONN_SRCCLKENA_3_FPM_SHFT     17
#define CONN_INFRA_CFG_RC_STATUS_CONN_SRCCLKENA_3_BBLPM_ADDR   CONN_INFRA_CFG_RC_STATUS_ADDR
#define CONN_INFRA_CFG_RC_STATUS_CONN_SRCCLKENA_3_BBLPM_MASK   0x00010000
#define CONN_INFRA_CFG_RC_STATUS_CONN_SRCCLKENA_3_BBLPM_SHFT   16
#define CONN_INFRA_CFG_RC_STATUS_CONN_SRCCLKENA_2_FPM_ACK_ADDR CONN_INFRA_CFG_RC_STATUS_ADDR
#define CONN_INFRA_CFG_RC_STATUS_CONN_SRCCLKENA_2_FPM_ACK_MASK 0x00008000
#define CONN_INFRA_CFG_RC_STATUS_CONN_SRCCLKENA_2_FPM_ACK_SHFT 15
#define CONN_INFRA_CFG_RC_STATUS_CONN_SRCCLKENA_2_BBLPM_ACK_ADDR CONN_INFRA_CFG_RC_STATUS_ADDR
#define CONN_INFRA_CFG_RC_STATUS_CONN_SRCCLKENA_2_BBLPM_ACK_MASK 0x00004000
#define CONN_INFRA_CFG_RC_STATUS_CONN_SRCCLKENA_2_BBLPM_ACK_SHFT 14
#define CONN_INFRA_CFG_RC_STATUS_CONN_SRCCLKENA_2_FPM_ADDR     CONN_INFRA_CFG_RC_STATUS_ADDR
#define CONN_INFRA_CFG_RC_STATUS_CONN_SRCCLKENA_2_FPM_MASK     0x00002000
#define CONN_INFRA_CFG_RC_STATUS_CONN_SRCCLKENA_2_FPM_SHFT     13
#define CONN_INFRA_CFG_RC_STATUS_CONN_SRCCLKENA_2_BBLPM_ADDR   CONN_INFRA_CFG_RC_STATUS_ADDR
#define CONN_INFRA_CFG_RC_STATUS_CONN_SRCCLKENA_2_BBLPM_MASK   0x00001000
#define CONN_INFRA_CFG_RC_STATUS_CONN_SRCCLKENA_2_BBLPM_SHFT   12
#define CONN_INFRA_CFG_RC_STATUS_CONN_SRCCLKENA_1_FPM_ACK_ADDR CONN_INFRA_CFG_RC_STATUS_ADDR
#define CONN_INFRA_CFG_RC_STATUS_CONN_SRCCLKENA_1_FPM_ACK_MASK 0x00000800
#define CONN_INFRA_CFG_RC_STATUS_CONN_SRCCLKENA_1_FPM_ACK_SHFT 11
#define CONN_INFRA_CFG_RC_STATUS_CONN_SRCCLKENA_1_BBLPM_ACK_ADDR CONN_INFRA_CFG_RC_STATUS_ADDR
#define CONN_INFRA_CFG_RC_STATUS_CONN_SRCCLKENA_1_BBLPM_ACK_MASK 0x00000400
#define CONN_INFRA_CFG_RC_STATUS_CONN_SRCCLKENA_1_BBLPM_ACK_SHFT 10
#define CONN_INFRA_CFG_RC_STATUS_CONN_SRCCLKENA_1_FPM_ADDR     CONN_INFRA_CFG_RC_STATUS_ADDR
#define CONN_INFRA_CFG_RC_STATUS_CONN_SRCCLKENA_1_FPM_MASK     0x00000200
#define CONN_INFRA_CFG_RC_STATUS_CONN_SRCCLKENA_1_FPM_SHFT     9
#define CONN_INFRA_CFG_RC_STATUS_CONN_SRCCLKENA_1_BBLPM_ADDR   CONN_INFRA_CFG_RC_STATUS_ADDR
#define CONN_INFRA_CFG_RC_STATUS_CONN_SRCCLKENA_1_BBLPM_MASK   0x00000100
#define CONN_INFRA_CFG_RC_STATUS_CONN_SRCCLKENA_1_BBLPM_SHFT   8
#define CONN_INFRA_CFG_RC_STATUS_CONN_SRCCLKENA_0_FPM_ACK_ADDR CONN_INFRA_CFG_RC_STATUS_ADDR
#define CONN_INFRA_CFG_RC_STATUS_CONN_SRCCLKENA_0_FPM_ACK_MASK 0x00000080
#define CONN_INFRA_CFG_RC_STATUS_CONN_SRCCLKENA_0_FPM_ACK_SHFT 7
#define CONN_INFRA_CFG_RC_STATUS_CONN_SRCCLKENA_0_BBLPM_ACK_ADDR CONN_INFRA_CFG_RC_STATUS_ADDR
#define CONN_INFRA_CFG_RC_STATUS_CONN_SRCCLKENA_0_BBLPM_ACK_MASK 0x00000040
#define CONN_INFRA_CFG_RC_STATUS_CONN_SRCCLKENA_0_BBLPM_ACK_SHFT 6
#define CONN_INFRA_CFG_RC_STATUS_CONN_SRCCLKENA_0_FPM_ADDR     CONN_INFRA_CFG_RC_STATUS_ADDR
#define CONN_INFRA_CFG_RC_STATUS_CONN_SRCCLKENA_0_FPM_MASK     0x00000020
#define CONN_INFRA_CFG_RC_STATUS_CONN_SRCCLKENA_0_FPM_SHFT     5
#define CONN_INFRA_CFG_RC_STATUS_CONN_SRCCLKENA_0_BBLPM_ADDR   CONN_INFRA_CFG_RC_STATUS_ADDR
#define CONN_INFRA_CFG_RC_STATUS_CONN_SRCCLKENA_0_BBLPM_MASK   0x00000010
#define CONN_INFRA_CFG_RC_STATUS_CONN_SRCCLKENA_0_BBLPM_SHFT   4
#define CONN_INFRA_CFG_RC_STATUS_CONN_INFRA_OSC_ON_D1_ADDR     CONN_INFRA_CFG_RC_STATUS_ADDR
#define CONN_INFRA_CFG_RC_STATUS_CONN_INFRA_OSC_ON_D1_MASK     0x00000008
#define CONN_INFRA_CFG_RC_STATUS_CONN_INFRA_OSC_ON_D1_SHFT     3
#define CONN_INFRA_CFG_RC_STATUS_WFSYS_OSC_ON_D1_ADDR          CONN_INFRA_CFG_RC_STATUS_ADDR
#define CONN_INFRA_CFG_RC_STATUS_WFSYS_OSC_ON_D1_MASK          0x00000004
#define CONN_INFRA_CFG_RC_STATUS_WFSYS_OSC_ON_D1_SHFT          2
#define CONN_INFRA_CFG_RC_STATUS_BTSYS_OSC_ON_D1_ADDR          CONN_INFRA_CFG_RC_STATUS_ADDR
#define CONN_INFRA_CFG_RC_STATUS_BTSYS_OSC_ON_D1_MASK          0x00000002
#define CONN_INFRA_CFG_RC_STATUS_BTSYS_OSC_ON_D1_SHFT          1
#define CONN_INFRA_CFG_RC_STATUS_GPSSYS_OSC_ON_D1_ADDR         CONN_INFRA_CFG_RC_STATUS_ADDR
#define CONN_INFRA_CFG_RC_STATUS_GPSSYS_OSC_ON_D1_MASK         0x00000001
#define CONN_INFRA_CFG_RC_STATUS_GPSSYS_OSC_ON_D1_SHFT         0

#define CONN_INFRA_CFG_RC_CTL_0_RC_RSV_ADDR                    CONN_INFRA_CFG_RC_CTL_0_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_RC_RSV_MASK                    0xE0000000
#define CONN_INFRA_CFG_RC_CTL_0_RC_RSV_SHFT                    29
#define CONN_INFRA_CFG_RC_CTL_0_CONN_BT_ONLY_RC_OUT_EN_ADDR    CONN_INFRA_CFG_RC_CTL_0_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_CONN_BT_ONLY_RC_OUT_EN_MASK    0x10000000
#define CONN_INFRA_CFG_RC_CTL_0_CONN_BT_ONLY_RC_OUT_EN_SHFT    28
#define CONN_INFRA_CFG_RC_CTL_0_CONN_RC3_SEL_ADDR              CONN_INFRA_CFG_RC_CTL_0_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_CONN_RC3_SEL_MASK              0x08000000
#define CONN_INFRA_CFG_RC_CTL_0_CONN_RC3_SEL_SHFT              27
#define CONN_INFRA_CFG_RC_CTL_0_CONN_RC1_SEL_ADDR              CONN_INFRA_CFG_RC_CTL_0_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_CONN_RC1_SEL_MASK              0x04000000
#define CONN_INFRA_CFG_RC_CTL_0_CONN_RC1_SEL_SHFT              26
#define CONN_INFRA_CFG_RC_CTL_0_CONN_BT_ONLY_WGF_RC_EN_ADDR    CONN_INFRA_CFG_RC_CTL_0_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_CONN_BT_ONLY_WGF_RC_EN_MASK    0x02000000
#define CONN_INFRA_CFG_RC_CTL_0_CONN_BT_ONLY_WGF_RC_EN_SHFT    25
#define CONN_INFRA_CFG_RC_CTL_0_CONN_INFRA_VCORE_RST_B_SEL_ADDR CONN_INFRA_CFG_RC_CTL_0_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_CONN_INFRA_VCORE_RST_B_SEL_MASK 0x01000000
#define CONN_INFRA_CFG_RC_CTL_0_CONN_INFRA_VCORE_RST_B_SEL_SHFT 24
#define CONN_INFRA_CFG_RC_CTL_0_WFSYS_VCORE_RST_B_SEL_ADDR     CONN_INFRA_CFG_RC_CTL_0_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_WFSYS_VCORE_RST_B_SEL_MASK     0x00800000
#define CONN_INFRA_CFG_RC_CTL_0_WFSYS_VCORE_RST_B_SEL_SHFT     23
#define CONN_INFRA_CFG_RC_CTL_0_BTSYS_VCORE_RST_B_SEL_ADDR     CONN_INFRA_CFG_RC_CTL_0_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_BTSYS_VCORE_RST_B_SEL_MASK     0x00400000
#define CONN_INFRA_CFG_RC_CTL_0_BTSYS_VCORE_RST_B_SEL_SHFT     22
#define CONN_INFRA_CFG_RC_CTL_0_GPSSYS_VCORE_RST_B_SEL_ADDR    CONN_INFRA_CFG_RC_CTL_0_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_GPSSYS_VCORE_RST_B_SEL_MASK    0x00200000
#define CONN_INFRA_CFG_RC_CTL_0_GPSSYS_VCORE_RST_B_SEL_SHFT    21
#define CONN_INFRA_CFG_RC_CTL_0_CONN_BT_ONLY_RC_EN_ADDR        CONN_INFRA_CFG_RC_CTL_0_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_CONN_BT_ONLY_RC_EN_MASK        0x00100000
#define CONN_INFRA_CFG_RC_CTL_0_CONN_BT_ONLY_RC_EN_SHFT        20
#define CONN_INFRA_CFG_RC_CTL_0_CONN_INFRA_OSC_RST_B_SEL_ADDR  CONN_INFRA_CFG_RC_CTL_0_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_CONN_INFRA_OSC_RST_B_SEL_MASK  0x00080000
#define CONN_INFRA_CFG_RC_CTL_0_CONN_INFRA_OSC_RST_B_SEL_SHFT  19
#define CONN_INFRA_CFG_RC_CTL_0_WFSYS_OSC_RST_B_SEL_ADDR       CONN_INFRA_CFG_RC_CTL_0_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_WFSYS_OSC_RST_B_SEL_MASK       0x00040000
#define CONN_INFRA_CFG_RC_CTL_0_WFSYS_OSC_RST_B_SEL_SHFT       18
#define CONN_INFRA_CFG_RC_CTL_0_BTSYS_OSC_RST_B_SEL_ADDR       CONN_INFRA_CFG_RC_CTL_0_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_BTSYS_OSC_RST_B_SEL_MASK       0x00020000
#define CONN_INFRA_CFG_RC_CTL_0_BTSYS_OSC_RST_B_SEL_SHFT       17
#define CONN_INFRA_CFG_RC_CTL_0_GPSSYS_OSC_RST_B_SEL_ADDR      CONN_INFRA_CFG_RC_CTL_0_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_GPSSYS_OSC_RST_B_SEL_MASK      0x00010000
#define CONN_INFRA_CFG_RC_CTL_0_GPSSYS_OSC_RST_B_SEL_SHFT      16
#define CONN_INFRA_CFG_RC_CTL_0_CONN_INFRA_BBLPM_EN_ADDR       CONN_INFRA_CFG_RC_CTL_0_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_CONN_INFRA_BBLPM_EN_MASK       0x00008000
#define CONN_INFRA_CFG_RC_CTL_0_CONN_INFRA_BBLPM_EN_SHFT       15
#define CONN_INFRA_CFG_RC_CTL_0_WFSYS_BBLPM_EN_ADDR            CONN_INFRA_CFG_RC_CTL_0_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_WFSYS_BBLPM_EN_MASK            0x00004000
#define CONN_INFRA_CFG_RC_CTL_0_WFSYS_BBLPM_EN_SHFT            14
#define CONN_INFRA_CFG_RC_CTL_0_BTSYS_BBLPM_EN_ADDR            CONN_INFRA_CFG_RC_CTL_0_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_BTSYS_BBLPM_EN_MASK            0x00002000
#define CONN_INFRA_CFG_RC_CTL_0_BTSYS_BBLPM_EN_SHFT            13
#define CONN_INFRA_CFG_RC_CTL_0_GPSSYS_BBLPM_EN_ADDR           CONN_INFRA_CFG_RC_CTL_0_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_GPSSYS_BBLPM_EN_MASK           0x00001000
#define CONN_INFRA_CFG_RC_CTL_0_GPSSYS_BBLPM_EN_SHFT           12
#define CONN_INFRA_CFG_RC_CTL_0_SW_CONN_INFRA_OSC_ON_RC_ADDR   CONN_INFRA_CFG_RC_CTL_0_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_SW_CONN_INFRA_OSC_ON_RC_MASK   0x00000800
#define CONN_INFRA_CFG_RC_CTL_0_SW_CONN_INFRA_OSC_ON_RC_SHFT   11
#define CONN_INFRA_CFG_RC_CTL_0_SW_WFSYS_OSC_ON_RC_ADDR        CONN_INFRA_CFG_RC_CTL_0_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_SW_WFSYS_OSC_ON_RC_MASK        0x00000400
#define CONN_INFRA_CFG_RC_CTL_0_SW_WFSYS_OSC_ON_RC_SHFT        10
#define CONN_INFRA_CFG_RC_CTL_0_SW_BTSYS_OSC_ON_RC_ADDR        CONN_INFRA_CFG_RC_CTL_0_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_SW_BTSYS_OSC_ON_RC_MASK        0x00000200
#define CONN_INFRA_CFG_RC_CTL_0_SW_BTSYS_OSC_ON_RC_SHFT        9
#define CONN_INFRA_CFG_RC_CTL_0_SW_GPSSYS_OSC_ON_RC_ADDR       CONN_INFRA_CFG_RC_CTL_0_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_SW_GPSSYS_OSC_ON_RC_MASK       0x00000100
#define CONN_INFRA_CFG_RC_CTL_0_SW_GPSSYS_OSC_ON_RC_SHFT       8
#define CONN_INFRA_CFG_RC_CTL_0_CONN_INFRA_OSC_RC_EN_ADDR      CONN_INFRA_CFG_RC_CTL_0_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_CONN_INFRA_OSC_RC_EN_MASK      0x00000080
#define CONN_INFRA_CFG_RC_CTL_0_CONN_INFRA_OSC_RC_EN_SHFT      7
#define CONN_INFRA_CFG_RC_CTL_0_WFSYS_OSC_RC_EN_ADDR           CONN_INFRA_CFG_RC_CTL_0_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_WFSYS_OSC_RC_EN_MASK           0x00000040
#define CONN_INFRA_CFG_RC_CTL_0_WFSYS_OSC_RC_EN_SHFT           6
#define CONN_INFRA_CFG_RC_CTL_0_BTSYS_OSC_RC_EN_ADDR           CONN_INFRA_CFG_RC_CTL_0_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_BTSYS_OSC_RC_EN_MASK           0x00000020
#define CONN_INFRA_CFG_RC_CTL_0_BTSYS_OSC_RC_EN_SHFT           5
#define CONN_INFRA_CFG_RC_CTL_0_GPSSYS_OSC_RC_EN_ADDR          CONN_INFRA_CFG_RC_CTL_0_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_GPSSYS_OSC_RC_EN_MASK          0x00000010
#define CONN_INFRA_CFG_RC_CTL_0_GPSSYS_OSC_RC_EN_SHFT          4
#define CONN_INFRA_CFG_RC_CTL_0_SW_OSC_ON_ALL_ADDR             CONN_INFRA_CFG_RC_CTL_0_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_SW_OSC_ON_ALL_MASK             0x00000002
#define CONN_INFRA_CFG_RC_CTL_0_SW_OSC_ON_ALL_SHFT             1
#define CONN_INFRA_CFG_RC_CTL_0_OSC_LEGACY_EN_ADDR             CONN_INFRA_CFG_RC_CTL_0_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_OSC_LEGACY_EN_MASK             0x00000001
#define CONN_INFRA_CFG_RC_CTL_0_OSC_LEGACY_EN_SHFT             0

#define CONN_INFRA_CFG_RC_CTL_0_GPS_RC_GPS_RSV_ADDR            CONN_INFRA_CFG_RC_CTL_0_GPS_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_GPS_RC_GPS_RSV_MASK            0xF0000000
#define CONN_INFRA_CFG_RC_CTL_0_GPS_RC_GPS_RSV_SHFT            28
#define CONN_INFRA_CFG_RC_CTL_0_GPS_GPS_OSC_ACK_BP_MEM_PON_ADDR CONN_INFRA_CFG_RC_CTL_0_GPS_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_GPS_GPS_OSC_ACK_BP_MEM_PON_MASK 0x08000000
#define CONN_INFRA_CFG_RC_CTL_0_GPS_GPS_OSC_ACK_BP_MEM_PON_SHFT 27
#define CONN_INFRA_CFG_RC_CTL_0_GPS_GPS_OSC_ACK_BP_PWR_ACK_ADDR CONN_INFRA_CFG_RC_CTL_0_GPS_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_GPS_GPS_OSC_ACK_BP_PWR_ACK_MASK 0x04000000
#define CONN_INFRA_CFG_RC_CTL_0_GPS_GPS_OSC_ACK_BP_PWR_ACK_SHFT 26
#define CONN_INFRA_CFG_RC_CTL_0_GPS_HW_OSC_RDY_0_ADDR          CONN_INFRA_CFG_RC_CTL_0_GPS_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_GPS_HW_OSC_RDY_0_MASK          0x02000000
#define CONN_INFRA_CFG_RC_CTL_0_GPS_HW_OSC_RDY_0_SHFT          25
#define CONN_INFRA_CFG_RC_CTL_0_GPS_HW_DA_WBG_EN_XBUF_0_ADDR   CONN_INFRA_CFG_RC_CTL_0_GPS_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_GPS_HW_DA_WBG_EN_XBUF_0_MASK   0x01000000
#define CONN_INFRA_CFG_RC_CTL_0_GPS_HW_DA_WBG_EN_XBUF_0_SHFT   24
#define CONN_INFRA_CFG_RC_CTL_0_GPS_HW_DA_WBG_EN_BG_0_ADDR     CONN_INFRA_CFG_RC_CTL_0_GPS_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_GPS_HW_DA_WBG_EN_BG_0_MASK     0x00800000
#define CONN_INFRA_CFG_RC_CTL_0_GPS_HW_DA_WBG_EN_BG_0_SHFT     23
#define CONN_INFRA_CFG_RC_CTL_0_GPS_HW_VCORE_RDY_0_ADDR        CONN_INFRA_CFG_RC_CTL_0_GPS_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_GPS_HW_VCORE_RDY_0_MASK        0x00400000
#define CONN_INFRA_CFG_RC_CTL_0_GPS_HW_VCORE_RDY_0_SHFT        22
#define CONN_INFRA_CFG_RC_CTL_0_GPS_HW_CONN_SRCCLKENA_0_ADDR   CONN_INFRA_CFG_RC_CTL_0_GPS_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_GPS_HW_CONN_SRCCLKENA_0_MASK   0x00200000
#define CONN_INFRA_CFG_RC_CTL_0_GPS_HW_CONN_SRCCLKENA_0_SHFT   21
#define CONN_INFRA_CFG_RC_CTL_0_GPS_XO_STATE_0_ADDR            CONN_INFRA_CFG_RC_CTL_0_GPS_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_GPS_XO_STATE_0_MASK            0x001E0000
#define CONN_INFRA_CFG_RC_CTL_0_GPS_XO_STATE_0_SHFT            17
#define CONN_INFRA_CFG_RC_CTL_0_GPS_XO_EN_0_ADDR               CONN_INFRA_CFG_RC_CTL_0_GPS_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_GPS_XO_EN_0_MASK               0x00010000
#define CONN_INFRA_CFG_RC_CTL_0_GPS_XO_EN_0_SHFT               16
#define CONN_INFRA_CFG_RC_CTL_0_GPS_ACK_FOR_XO_STATE_MASK_0_ADDR CONN_INFRA_CFG_RC_CTL_0_GPS_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_GPS_ACK_FOR_XO_STATE_MASK_0_MASK 0x00008000
#define CONN_INFRA_CFG_RC_CTL_0_GPS_ACK_FOR_XO_STATE_MASK_0_SHFT 15
#define CONN_INFRA_CFG_RC_CTL_0_GPS_SW_OSC_RDY_0_ADDR          CONN_INFRA_CFG_RC_CTL_0_GPS_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_GPS_SW_OSC_RDY_0_MASK          0x00001000
#define CONN_INFRA_CFG_RC_CTL_0_GPS_SW_OSC_RDY_0_SHFT          12
#define CONN_INFRA_CFG_RC_CTL_0_GPS_SW_VCORE_RDY_0_ADDR        CONN_INFRA_CFG_RC_CTL_0_GPS_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_GPS_SW_VCORE_RDY_0_MASK        0x00000800
#define CONN_INFRA_CFG_RC_CTL_0_GPS_SW_VCORE_RDY_0_SHFT        11
#define CONN_INFRA_CFG_RC_CTL_0_GPS_SW_DA_WBG_EN_XBUF_0_ADDR   CONN_INFRA_CFG_RC_CTL_0_GPS_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_GPS_SW_DA_WBG_EN_XBUF_0_MASK   0x00000400
#define CONN_INFRA_CFG_RC_CTL_0_GPS_SW_DA_WBG_EN_XBUF_0_SHFT   10
#define CONN_INFRA_CFG_RC_CTL_0_GPS_SW_DA_WBG_EN_BG_0_ADDR     CONN_INFRA_CFG_RC_CTL_0_GPS_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_GPS_SW_DA_WBG_EN_BG_0_MASK     0x00000200
#define CONN_INFRA_CFG_RC_CTL_0_GPS_SW_DA_WBG_EN_BG_0_SHFT     9
#define CONN_INFRA_CFG_RC_CTL_0_GPS_SW_CONN_SRCCLKENA_0_ADDR   CONN_INFRA_CFG_RC_CTL_0_GPS_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_GPS_SW_CONN_SRCCLKENA_0_MASK   0x00000100
#define CONN_INFRA_CFG_RC_CTL_0_GPS_SW_CONN_SRCCLKENA_0_SHFT   8
#define CONN_INFRA_CFG_RC_CTL_0_GPS_SWCTL_OSC_RDY_0_ADDR       CONN_INFRA_CFG_RC_CTL_0_GPS_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_GPS_SWCTL_OSC_RDY_0_MASK       0x00000010
#define CONN_INFRA_CFG_RC_CTL_0_GPS_SWCTL_OSC_RDY_0_SHFT       4
#define CONN_INFRA_CFG_RC_CTL_0_GPS_SWCTL_VCORE_RDY_0_ADDR     CONN_INFRA_CFG_RC_CTL_0_GPS_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_GPS_SWCTL_VCORE_RDY_0_MASK     0x00000008
#define CONN_INFRA_CFG_RC_CTL_0_GPS_SWCTL_VCORE_RDY_0_SHFT     3
#define CONN_INFRA_CFG_RC_CTL_0_GPS_SWCTL_DA_WBG_EN_XBUF_0_ADDR CONN_INFRA_CFG_RC_CTL_0_GPS_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_GPS_SWCTL_DA_WBG_EN_XBUF_0_MASK 0x00000004
#define CONN_INFRA_CFG_RC_CTL_0_GPS_SWCTL_DA_WBG_EN_XBUF_0_SHFT 2
#define CONN_INFRA_CFG_RC_CTL_0_GPS_SWCTL_DA_WBG_EN_BG_0_ADDR  CONN_INFRA_CFG_RC_CTL_0_GPS_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_GPS_SWCTL_DA_WBG_EN_BG_0_MASK  0x00000002
#define CONN_INFRA_CFG_RC_CTL_0_GPS_SWCTL_DA_WBG_EN_BG_0_SHFT  1
#define CONN_INFRA_CFG_RC_CTL_0_GPS_SWCTL_CONN_SRCCLKENA_0_ADDR CONN_INFRA_CFG_RC_CTL_0_GPS_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_GPS_SWCTL_CONN_SRCCLKENA_0_MASK 0x00000001
#define CONN_INFRA_CFG_RC_CTL_0_GPS_SWCTL_CONN_SRCCLKENA_0_SHFT 0

#define CONN_INFRA_CFG_RC_CTL_1_GPS_XO_VCORE_OFF_STABLE_TIME_0_ADDR CONN_INFRA_CFG_RC_CTL_1_GPS_ADDR
#define CONN_INFRA_CFG_RC_CTL_1_GPS_XO_VCORE_OFF_STABLE_TIME_0_MASK 0xFF000000
#define CONN_INFRA_CFG_RC_CTL_1_GPS_XO_VCORE_OFF_STABLE_TIME_0_SHFT 24
#define CONN_INFRA_CFG_RC_CTL_1_GPS_XO_BG_STABLE_TIME_0_ADDR   CONN_INFRA_CFG_RC_CTL_1_GPS_ADDR
#define CONN_INFRA_CFG_RC_CTL_1_GPS_XO_BG_STABLE_TIME_0_MASK   0x00FF0000
#define CONN_INFRA_CFG_RC_CTL_1_GPS_XO_BG_STABLE_TIME_0_SHFT   16
#define CONN_INFRA_CFG_RC_CTL_1_GPS_XO_INI_STABLE_TIME_0_ADDR  CONN_INFRA_CFG_RC_CTL_1_GPS_ADDR
#define CONN_INFRA_CFG_RC_CTL_1_GPS_XO_INI_STABLE_TIME_0_MASK  0x0000FF00
#define CONN_INFRA_CFG_RC_CTL_1_GPS_XO_INI_STABLE_TIME_0_SHFT  8
#define CONN_INFRA_CFG_RC_CTL_1_GPS_XO_VCORE_RDY_STABLE_TIME_0_ADDR CONN_INFRA_CFG_RC_CTL_1_GPS_ADDR
#define CONN_INFRA_CFG_RC_CTL_1_GPS_XO_VCORE_RDY_STABLE_TIME_0_MASK 0x000000FF
#define CONN_INFRA_CFG_RC_CTL_1_GPS_XO_VCORE_RDY_STABLE_TIME_0_SHFT 0

#define CONN_INFRA_CFG_RC_CTL_0_BT_RC_BT_RSV_ADDR              CONN_INFRA_CFG_RC_CTL_0_BT_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_BT_RC_BT_RSV_MASK              0xF0000000
#define CONN_INFRA_CFG_RC_CTL_0_BT_RC_BT_RSV_SHFT              28
#define CONN_INFRA_CFG_RC_CTL_0_BT_BT_OSC_ACK_BP_MEM_PON_ADDR  CONN_INFRA_CFG_RC_CTL_0_BT_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_BT_BT_OSC_ACK_BP_MEM_PON_MASK  0x08000000
#define CONN_INFRA_CFG_RC_CTL_0_BT_BT_OSC_ACK_BP_MEM_PON_SHFT  27
#define CONN_INFRA_CFG_RC_CTL_0_BT_BT_OSC_ACK_BP_PWR_ACK_ADDR  CONN_INFRA_CFG_RC_CTL_0_BT_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_BT_BT_OSC_ACK_BP_PWR_ACK_MASK  0x04000000
#define CONN_INFRA_CFG_RC_CTL_0_BT_BT_OSC_ACK_BP_PWR_ACK_SHFT  26
#define CONN_INFRA_CFG_RC_CTL_0_BT_HW_OSC_RDY_1_ADDR           CONN_INFRA_CFG_RC_CTL_0_BT_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_BT_HW_OSC_RDY_1_MASK           0x02000000
#define CONN_INFRA_CFG_RC_CTL_0_BT_HW_OSC_RDY_1_SHFT           25
#define CONN_INFRA_CFG_RC_CTL_0_BT_HW_DA_WBG_EN_XBUF_1_ADDR    CONN_INFRA_CFG_RC_CTL_0_BT_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_BT_HW_DA_WBG_EN_XBUF_1_MASK    0x01000000
#define CONN_INFRA_CFG_RC_CTL_0_BT_HW_DA_WBG_EN_XBUF_1_SHFT    24
#define CONN_INFRA_CFG_RC_CTL_0_BT_HW_DA_WBG_EN_BG_1_ADDR      CONN_INFRA_CFG_RC_CTL_0_BT_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_BT_HW_DA_WBG_EN_BG_1_MASK      0x00800000
#define CONN_INFRA_CFG_RC_CTL_0_BT_HW_DA_WBG_EN_BG_1_SHFT      23
#define CONN_INFRA_CFG_RC_CTL_0_BT_HW_VCORE_RDY_1_ADDR         CONN_INFRA_CFG_RC_CTL_0_BT_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_BT_HW_VCORE_RDY_1_MASK         0x00400000
#define CONN_INFRA_CFG_RC_CTL_0_BT_HW_VCORE_RDY_1_SHFT         22
#define CONN_INFRA_CFG_RC_CTL_0_BT_HW_CONN_SRCCLKENA_1_ADDR    CONN_INFRA_CFG_RC_CTL_0_BT_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_BT_HW_CONN_SRCCLKENA_1_MASK    0x00200000
#define CONN_INFRA_CFG_RC_CTL_0_BT_HW_CONN_SRCCLKENA_1_SHFT    21
#define CONN_INFRA_CFG_RC_CTL_0_BT_XO_STATE_1_ADDR             CONN_INFRA_CFG_RC_CTL_0_BT_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_BT_XO_STATE_1_MASK             0x001E0000
#define CONN_INFRA_CFG_RC_CTL_0_BT_XO_STATE_1_SHFT             17
#define CONN_INFRA_CFG_RC_CTL_0_BT_XO_EN_1_ADDR                CONN_INFRA_CFG_RC_CTL_0_BT_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_BT_XO_EN_1_MASK                0x00010000
#define CONN_INFRA_CFG_RC_CTL_0_BT_XO_EN_1_SHFT                16
#define CONN_INFRA_CFG_RC_CTL_0_BT_ACK_FOR_XO_STATE_MASK_1_ADDR CONN_INFRA_CFG_RC_CTL_0_BT_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_BT_ACK_FOR_XO_STATE_MASK_1_MASK 0x00008000
#define CONN_INFRA_CFG_RC_CTL_0_BT_ACK_FOR_XO_STATE_MASK_1_SHFT 15
#define CONN_INFRA_CFG_RC_CTL_0_BT_SW_OSC_RDY_1_ADDR           CONN_INFRA_CFG_RC_CTL_0_BT_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_BT_SW_OSC_RDY_1_MASK           0x00001000
#define CONN_INFRA_CFG_RC_CTL_0_BT_SW_OSC_RDY_1_SHFT           12
#define CONN_INFRA_CFG_RC_CTL_0_BT_SW_VCORE_RDY_1_ADDR         CONN_INFRA_CFG_RC_CTL_0_BT_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_BT_SW_VCORE_RDY_1_MASK         0x00000800
#define CONN_INFRA_CFG_RC_CTL_0_BT_SW_VCORE_RDY_1_SHFT         11
#define CONN_INFRA_CFG_RC_CTL_0_BT_SW_DA_WBG_EN_XBUF_1_ADDR    CONN_INFRA_CFG_RC_CTL_0_BT_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_BT_SW_DA_WBG_EN_XBUF_1_MASK    0x00000400
#define CONN_INFRA_CFG_RC_CTL_0_BT_SW_DA_WBG_EN_XBUF_1_SHFT    10
#define CONN_INFRA_CFG_RC_CTL_0_BT_SW_DA_WBG_EN_BG_1_ADDR      CONN_INFRA_CFG_RC_CTL_0_BT_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_BT_SW_DA_WBG_EN_BG_1_MASK      0x00000200
#define CONN_INFRA_CFG_RC_CTL_0_BT_SW_DA_WBG_EN_BG_1_SHFT      9
#define CONN_INFRA_CFG_RC_CTL_0_BT_SW_CONN_SRCCLKENA_1_ADDR    CONN_INFRA_CFG_RC_CTL_0_BT_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_BT_SW_CONN_SRCCLKENA_1_MASK    0x00000100
#define CONN_INFRA_CFG_RC_CTL_0_BT_SW_CONN_SRCCLKENA_1_SHFT    8
#define CONN_INFRA_CFG_RC_CTL_0_BT_SWCTL_OSC_RDY_1_ADDR        CONN_INFRA_CFG_RC_CTL_0_BT_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_BT_SWCTL_OSC_RDY_1_MASK        0x00000010
#define CONN_INFRA_CFG_RC_CTL_0_BT_SWCTL_OSC_RDY_1_SHFT        4
#define CONN_INFRA_CFG_RC_CTL_0_BT_SWCTL_VCORE_RDY_1_ADDR      CONN_INFRA_CFG_RC_CTL_0_BT_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_BT_SWCTL_VCORE_RDY_1_MASK      0x00000008
#define CONN_INFRA_CFG_RC_CTL_0_BT_SWCTL_VCORE_RDY_1_SHFT      3
#define CONN_INFRA_CFG_RC_CTL_0_BT_SWCTL_DA_WBG_EN_XBUF_1_ADDR CONN_INFRA_CFG_RC_CTL_0_BT_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_BT_SWCTL_DA_WBG_EN_XBUF_1_MASK 0x00000004
#define CONN_INFRA_CFG_RC_CTL_0_BT_SWCTL_DA_WBG_EN_XBUF_1_SHFT 2
#define CONN_INFRA_CFG_RC_CTL_0_BT_SWCTL_DA_WBG_EN_BG_1_ADDR   CONN_INFRA_CFG_RC_CTL_0_BT_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_BT_SWCTL_DA_WBG_EN_BG_1_MASK   0x00000002
#define CONN_INFRA_CFG_RC_CTL_0_BT_SWCTL_DA_WBG_EN_BG_1_SHFT   1
#define CONN_INFRA_CFG_RC_CTL_0_BT_SWCTL_CONN_SRCCLKENA_1_ADDR CONN_INFRA_CFG_RC_CTL_0_BT_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_BT_SWCTL_CONN_SRCCLKENA_1_MASK 0x00000001
#define CONN_INFRA_CFG_RC_CTL_0_BT_SWCTL_CONN_SRCCLKENA_1_SHFT 0

#define CONN_INFRA_CFG_RC_CTL_1_BT_XO_VCORE_OFF_STABLE_TIME_1_ADDR CONN_INFRA_CFG_RC_CTL_1_BT_ADDR
#define CONN_INFRA_CFG_RC_CTL_1_BT_XO_VCORE_OFF_STABLE_TIME_1_MASK 0xFF000000
#define CONN_INFRA_CFG_RC_CTL_1_BT_XO_VCORE_OFF_STABLE_TIME_1_SHFT 24
#define CONN_INFRA_CFG_RC_CTL_1_BT_XO_BG_STABLE_TIME_1_ADDR    CONN_INFRA_CFG_RC_CTL_1_BT_ADDR
#define CONN_INFRA_CFG_RC_CTL_1_BT_XO_BG_STABLE_TIME_1_MASK    0x00FF0000
#define CONN_INFRA_CFG_RC_CTL_1_BT_XO_BG_STABLE_TIME_1_SHFT    16
#define CONN_INFRA_CFG_RC_CTL_1_BT_XO_INI_STABLE_TIME_1_ADDR   CONN_INFRA_CFG_RC_CTL_1_BT_ADDR
#define CONN_INFRA_CFG_RC_CTL_1_BT_XO_INI_STABLE_TIME_1_MASK   0x0000FF00
#define CONN_INFRA_CFG_RC_CTL_1_BT_XO_INI_STABLE_TIME_1_SHFT   8
#define CONN_INFRA_CFG_RC_CTL_1_BT_XO_VCORE_RDY_STABLE_TIME_1_ADDR CONN_INFRA_CFG_RC_CTL_1_BT_ADDR
#define CONN_INFRA_CFG_RC_CTL_1_BT_XO_VCORE_RDY_STABLE_TIME_1_MASK 0x000000FF
#define CONN_INFRA_CFG_RC_CTL_1_BT_XO_VCORE_RDY_STABLE_TIME_1_SHFT 0

#define CONN_INFRA_CFG_RC_CTL_0_WF_RC_WF_RSV_ADDR              CONN_INFRA_CFG_RC_CTL_0_WF_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_WF_RC_WF_RSV_MASK              0xF0000000
#define CONN_INFRA_CFG_RC_CTL_0_WF_RC_WF_RSV_SHFT              28
#define CONN_INFRA_CFG_RC_CTL_0_WF_WF_OSC_ACK_BP_MEM_PON_ADDR  CONN_INFRA_CFG_RC_CTL_0_WF_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_WF_WF_OSC_ACK_BP_MEM_PON_MASK  0x08000000
#define CONN_INFRA_CFG_RC_CTL_0_WF_WF_OSC_ACK_BP_MEM_PON_SHFT  27
#define CONN_INFRA_CFG_RC_CTL_0_WF_WF_OSC_ACK_BP_PWR_ACK_ADDR  CONN_INFRA_CFG_RC_CTL_0_WF_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_WF_WF_OSC_ACK_BP_PWR_ACK_MASK  0x04000000
#define CONN_INFRA_CFG_RC_CTL_0_WF_WF_OSC_ACK_BP_PWR_ACK_SHFT  26
#define CONN_INFRA_CFG_RC_CTL_0_WF_HW_OSC_RDY_2_ADDR           CONN_INFRA_CFG_RC_CTL_0_WF_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_WF_HW_OSC_RDY_2_MASK           0x02000000
#define CONN_INFRA_CFG_RC_CTL_0_WF_HW_OSC_RDY_2_SHFT           25
#define CONN_INFRA_CFG_RC_CTL_0_WF_HW_DA_WBG_EN_XBUF_2_ADDR    CONN_INFRA_CFG_RC_CTL_0_WF_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_WF_HW_DA_WBG_EN_XBUF_2_MASK    0x01000000
#define CONN_INFRA_CFG_RC_CTL_0_WF_HW_DA_WBG_EN_XBUF_2_SHFT    24
#define CONN_INFRA_CFG_RC_CTL_0_WF_HW_DA_WBG_EN_BG_2_ADDR      CONN_INFRA_CFG_RC_CTL_0_WF_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_WF_HW_DA_WBG_EN_BG_2_MASK      0x00800000
#define CONN_INFRA_CFG_RC_CTL_0_WF_HW_DA_WBG_EN_BG_2_SHFT      23
#define CONN_INFRA_CFG_RC_CTL_0_WF_HW_VCORE_RDY_2_ADDR         CONN_INFRA_CFG_RC_CTL_0_WF_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_WF_HW_VCORE_RDY_2_MASK         0x00400000
#define CONN_INFRA_CFG_RC_CTL_0_WF_HW_VCORE_RDY_2_SHFT         22
#define CONN_INFRA_CFG_RC_CTL_0_WF_HW_CONN_SRCCLKENA_2_ADDR    CONN_INFRA_CFG_RC_CTL_0_WF_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_WF_HW_CONN_SRCCLKENA_2_MASK    0x00200000
#define CONN_INFRA_CFG_RC_CTL_0_WF_HW_CONN_SRCCLKENA_2_SHFT    21
#define CONN_INFRA_CFG_RC_CTL_0_WF_XO_STATE_2_ADDR             CONN_INFRA_CFG_RC_CTL_0_WF_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_WF_XO_STATE_2_MASK             0x001E0000
#define CONN_INFRA_CFG_RC_CTL_0_WF_XO_STATE_2_SHFT             17
#define CONN_INFRA_CFG_RC_CTL_0_WF_XO_EN_2_ADDR                CONN_INFRA_CFG_RC_CTL_0_WF_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_WF_XO_EN_2_MASK                0x00010000
#define CONN_INFRA_CFG_RC_CTL_0_WF_XO_EN_2_SHFT                16
#define CONN_INFRA_CFG_RC_CTL_0_WF_ACK_FOR_XO_STATE_MASK_2_ADDR CONN_INFRA_CFG_RC_CTL_0_WF_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_WF_ACK_FOR_XO_STATE_MASK_2_MASK 0x00008000
#define CONN_INFRA_CFG_RC_CTL_0_WF_ACK_FOR_XO_STATE_MASK_2_SHFT 15
#define CONN_INFRA_CFG_RC_CTL_0_WF_SW_OSC_RDY_2_ADDR           CONN_INFRA_CFG_RC_CTL_0_WF_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_WF_SW_OSC_RDY_2_MASK           0x00001000
#define CONN_INFRA_CFG_RC_CTL_0_WF_SW_OSC_RDY_2_SHFT           12
#define CONN_INFRA_CFG_RC_CTL_0_WF_SW_VCORE_RDY_2_ADDR         CONN_INFRA_CFG_RC_CTL_0_WF_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_WF_SW_VCORE_RDY_2_MASK         0x00000800
#define CONN_INFRA_CFG_RC_CTL_0_WF_SW_VCORE_RDY_2_SHFT         11
#define CONN_INFRA_CFG_RC_CTL_0_WF_SW_DA_WBG_EN_XBUF_2_ADDR    CONN_INFRA_CFG_RC_CTL_0_WF_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_WF_SW_DA_WBG_EN_XBUF_2_MASK    0x00000400
#define CONN_INFRA_CFG_RC_CTL_0_WF_SW_DA_WBG_EN_XBUF_2_SHFT    10
#define CONN_INFRA_CFG_RC_CTL_0_WF_SW_DA_WBG_EN_BG_2_ADDR      CONN_INFRA_CFG_RC_CTL_0_WF_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_WF_SW_DA_WBG_EN_BG_2_MASK      0x00000200
#define CONN_INFRA_CFG_RC_CTL_0_WF_SW_DA_WBG_EN_BG_2_SHFT      9
#define CONN_INFRA_CFG_RC_CTL_0_WF_SW_CONN_SRCCLKENA_2_ADDR    CONN_INFRA_CFG_RC_CTL_0_WF_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_WF_SW_CONN_SRCCLKENA_2_MASK    0x00000100
#define CONN_INFRA_CFG_RC_CTL_0_WF_SW_CONN_SRCCLKENA_2_SHFT    8
#define CONN_INFRA_CFG_RC_CTL_0_WF_SWCTL_OSC_RDY_2_ADDR        CONN_INFRA_CFG_RC_CTL_0_WF_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_WF_SWCTL_OSC_RDY_2_MASK        0x00000010
#define CONN_INFRA_CFG_RC_CTL_0_WF_SWCTL_OSC_RDY_2_SHFT        4
#define CONN_INFRA_CFG_RC_CTL_0_WF_SWCTL_VCORE_RDY_2_ADDR      CONN_INFRA_CFG_RC_CTL_0_WF_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_WF_SWCTL_VCORE_RDY_2_MASK      0x00000008
#define CONN_INFRA_CFG_RC_CTL_0_WF_SWCTL_VCORE_RDY_2_SHFT      3
#define CONN_INFRA_CFG_RC_CTL_0_WF_SWCTL_DA_WBG_EN_XBUF_2_ADDR CONN_INFRA_CFG_RC_CTL_0_WF_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_WF_SWCTL_DA_WBG_EN_XBUF_2_MASK 0x00000004
#define CONN_INFRA_CFG_RC_CTL_0_WF_SWCTL_DA_WBG_EN_XBUF_2_SHFT 2
#define CONN_INFRA_CFG_RC_CTL_0_WF_SWCTL_DA_WBG_EN_BG_2_ADDR   CONN_INFRA_CFG_RC_CTL_0_WF_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_WF_SWCTL_DA_WBG_EN_BG_2_MASK   0x00000002
#define CONN_INFRA_CFG_RC_CTL_0_WF_SWCTL_DA_WBG_EN_BG_2_SHFT   1
#define CONN_INFRA_CFG_RC_CTL_0_WF_SWCTL_CONN_SRCCLKENA_2_ADDR CONN_INFRA_CFG_RC_CTL_0_WF_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_WF_SWCTL_CONN_SRCCLKENA_2_MASK 0x00000001
#define CONN_INFRA_CFG_RC_CTL_0_WF_SWCTL_CONN_SRCCLKENA_2_SHFT 0

#define CONN_INFRA_CFG_RC_CTL_1_WF_XO_VCORE_OFF_STABLE_TIME_2_ADDR CONN_INFRA_CFG_RC_CTL_1_WF_ADDR
#define CONN_INFRA_CFG_RC_CTL_1_WF_XO_VCORE_OFF_STABLE_TIME_2_MASK 0xFF000000
#define CONN_INFRA_CFG_RC_CTL_1_WF_XO_VCORE_OFF_STABLE_TIME_2_SHFT 24
#define CONN_INFRA_CFG_RC_CTL_1_WF_XO_BG_STABLE_TIME_2_ADDR    CONN_INFRA_CFG_RC_CTL_1_WF_ADDR
#define CONN_INFRA_CFG_RC_CTL_1_WF_XO_BG_STABLE_TIME_2_MASK    0x00FF0000
#define CONN_INFRA_CFG_RC_CTL_1_WF_XO_BG_STABLE_TIME_2_SHFT    16
#define CONN_INFRA_CFG_RC_CTL_1_WF_XO_INI_STABLE_TIME_2_ADDR   CONN_INFRA_CFG_RC_CTL_1_WF_ADDR
#define CONN_INFRA_CFG_RC_CTL_1_WF_XO_INI_STABLE_TIME_2_MASK   0x0000FF00
#define CONN_INFRA_CFG_RC_CTL_1_WF_XO_INI_STABLE_TIME_2_SHFT   8
#define CONN_INFRA_CFG_RC_CTL_1_WF_XO_VCORE_RDY_STABLE_TIME_2_ADDR CONN_INFRA_CFG_RC_CTL_1_WF_ADDR
#define CONN_INFRA_CFG_RC_CTL_1_WF_XO_VCORE_RDY_STABLE_TIME_2_MASK 0x000000FF
#define CONN_INFRA_CFG_RC_CTL_1_WF_XO_VCORE_RDY_STABLE_TIME_2_SHFT 0

#define CONN_INFRA_CFG_RC_CTL_0_TOP_RC_TOP_RSV_ADDR            CONN_INFRA_CFG_RC_CTL_0_TOP_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_TOP_RC_TOP_RSV_MASK            0xF0000000
#define CONN_INFRA_CFG_RC_CTL_0_TOP_RC_TOP_RSV_SHFT            28
#define CONN_INFRA_CFG_RC_CTL_0_TOP_TOP_OSC_ACK_BP_MEM_PON_ADDR CONN_INFRA_CFG_RC_CTL_0_TOP_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_TOP_TOP_OSC_ACK_BP_MEM_PON_MASK 0x08000000
#define CONN_INFRA_CFG_RC_CTL_0_TOP_TOP_OSC_ACK_BP_MEM_PON_SHFT 27
#define CONN_INFRA_CFG_RC_CTL_0_TOP_TOP_OSC_ACK_BP_PWR_ACK_ADDR CONN_INFRA_CFG_RC_CTL_0_TOP_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_TOP_TOP_OSC_ACK_BP_PWR_ACK_MASK 0x04000000
#define CONN_INFRA_CFG_RC_CTL_0_TOP_TOP_OSC_ACK_BP_PWR_ACK_SHFT 26
#define CONN_INFRA_CFG_RC_CTL_0_TOP_HW_OSC_RDY_3_ADDR          CONN_INFRA_CFG_RC_CTL_0_TOP_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_TOP_HW_OSC_RDY_3_MASK          0x02000000
#define CONN_INFRA_CFG_RC_CTL_0_TOP_HW_OSC_RDY_3_SHFT          25
#define CONN_INFRA_CFG_RC_CTL_0_TOP_HW_DA_WBG_EN_XBUF_3_ADDR   CONN_INFRA_CFG_RC_CTL_0_TOP_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_TOP_HW_DA_WBG_EN_XBUF_3_MASK   0x01000000
#define CONN_INFRA_CFG_RC_CTL_0_TOP_HW_DA_WBG_EN_XBUF_3_SHFT   24
#define CONN_INFRA_CFG_RC_CTL_0_TOP_HW_DA_WBG_EN_BG_3_ADDR     CONN_INFRA_CFG_RC_CTL_0_TOP_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_TOP_HW_DA_WBG_EN_BG_3_MASK     0x00800000
#define CONN_INFRA_CFG_RC_CTL_0_TOP_HW_DA_WBG_EN_BG_3_SHFT     23
#define CONN_INFRA_CFG_RC_CTL_0_TOP_HW_VCORE_RDY_3_ADDR        CONN_INFRA_CFG_RC_CTL_0_TOP_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_TOP_HW_VCORE_RDY_3_MASK        0x00400000
#define CONN_INFRA_CFG_RC_CTL_0_TOP_HW_VCORE_RDY_3_SHFT        22
#define CONN_INFRA_CFG_RC_CTL_0_TOP_HW_CONN_SRCCLKENA_3_ADDR   CONN_INFRA_CFG_RC_CTL_0_TOP_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_TOP_HW_CONN_SRCCLKENA_3_MASK   0x00200000
#define CONN_INFRA_CFG_RC_CTL_0_TOP_HW_CONN_SRCCLKENA_3_SHFT   21
#define CONN_INFRA_CFG_RC_CTL_0_TOP_XO_STATE_3_ADDR            CONN_INFRA_CFG_RC_CTL_0_TOP_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_TOP_XO_STATE_3_MASK            0x001E0000
#define CONN_INFRA_CFG_RC_CTL_0_TOP_XO_STATE_3_SHFT            17
#define CONN_INFRA_CFG_RC_CTL_0_TOP_XO_EN_3_ADDR               CONN_INFRA_CFG_RC_CTL_0_TOP_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_TOP_XO_EN_3_MASK               0x00010000
#define CONN_INFRA_CFG_RC_CTL_0_TOP_XO_EN_3_SHFT               16
#define CONN_INFRA_CFG_RC_CTL_0_TOP_ACK_FOR_XO_STATE_MASK_3_ADDR CONN_INFRA_CFG_RC_CTL_0_TOP_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_TOP_ACK_FOR_XO_STATE_MASK_3_MASK 0x00008000
#define CONN_INFRA_CFG_RC_CTL_0_TOP_ACK_FOR_XO_STATE_MASK_3_SHFT 15
#define CONN_INFRA_CFG_RC_CTL_0_TOP_SW_OSC_RDY_3_ADDR          CONN_INFRA_CFG_RC_CTL_0_TOP_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_TOP_SW_OSC_RDY_3_MASK          0x00001000
#define CONN_INFRA_CFG_RC_CTL_0_TOP_SW_OSC_RDY_3_SHFT          12
#define CONN_INFRA_CFG_RC_CTL_0_TOP_SW_VCORE_RDY_3_ADDR        CONN_INFRA_CFG_RC_CTL_0_TOP_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_TOP_SW_VCORE_RDY_3_MASK        0x00000800
#define CONN_INFRA_CFG_RC_CTL_0_TOP_SW_VCORE_RDY_3_SHFT        11
#define CONN_INFRA_CFG_RC_CTL_0_TOP_SW_DA_WBG_EN_XBUF_3_ADDR   CONN_INFRA_CFG_RC_CTL_0_TOP_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_TOP_SW_DA_WBG_EN_XBUF_3_MASK   0x00000400
#define CONN_INFRA_CFG_RC_CTL_0_TOP_SW_DA_WBG_EN_XBUF_3_SHFT   10
#define CONN_INFRA_CFG_RC_CTL_0_TOP_SW_DA_WBG_EN_BG_3_ADDR     CONN_INFRA_CFG_RC_CTL_0_TOP_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_TOP_SW_DA_WBG_EN_BG_3_MASK     0x00000200
#define CONN_INFRA_CFG_RC_CTL_0_TOP_SW_DA_WBG_EN_BG_3_SHFT     9
#define CONN_INFRA_CFG_RC_CTL_0_TOP_SW_CONN_SRCCLKENA_3_ADDR   CONN_INFRA_CFG_RC_CTL_0_TOP_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_TOP_SW_CONN_SRCCLKENA_3_MASK   0x00000100
#define CONN_INFRA_CFG_RC_CTL_0_TOP_SW_CONN_SRCCLKENA_3_SHFT   8
#define CONN_INFRA_CFG_RC_CTL_0_TOP_SWCTL_OSC_RDY_3_ADDR       CONN_INFRA_CFG_RC_CTL_0_TOP_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_TOP_SWCTL_OSC_RDY_3_MASK       0x00000010
#define CONN_INFRA_CFG_RC_CTL_0_TOP_SWCTL_OSC_RDY_3_SHFT       4
#define CONN_INFRA_CFG_RC_CTL_0_TOP_SWCTL_VCORE_RDY_3_ADDR     CONN_INFRA_CFG_RC_CTL_0_TOP_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_TOP_SWCTL_VCORE_RDY_3_MASK     0x00000008
#define CONN_INFRA_CFG_RC_CTL_0_TOP_SWCTL_VCORE_RDY_3_SHFT     3
#define CONN_INFRA_CFG_RC_CTL_0_TOP_SWCTL_DA_WBG_EN_XBUF_3_ADDR CONN_INFRA_CFG_RC_CTL_0_TOP_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_TOP_SWCTL_DA_WBG_EN_XBUF_3_MASK 0x00000004
#define CONN_INFRA_CFG_RC_CTL_0_TOP_SWCTL_DA_WBG_EN_XBUF_3_SHFT 2
#define CONN_INFRA_CFG_RC_CTL_0_TOP_SWCTL_DA_WBG_EN_BG_3_ADDR  CONN_INFRA_CFG_RC_CTL_0_TOP_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_TOP_SWCTL_DA_WBG_EN_BG_3_MASK  0x00000002
#define CONN_INFRA_CFG_RC_CTL_0_TOP_SWCTL_DA_WBG_EN_BG_3_SHFT  1
#define CONN_INFRA_CFG_RC_CTL_0_TOP_SWCTL_CONN_SRCCLKENA_3_ADDR CONN_INFRA_CFG_RC_CTL_0_TOP_ADDR
#define CONN_INFRA_CFG_RC_CTL_0_TOP_SWCTL_CONN_SRCCLKENA_3_MASK 0x00000001
#define CONN_INFRA_CFG_RC_CTL_0_TOP_SWCTL_CONN_SRCCLKENA_3_SHFT 0

#define CONN_INFRA_CFG_RC_CTL_1_TOP_XO_VCORE_OFF_STABLE_TIME_3_ADDR CONN_INFRA_CFG_RC_CTL_1_TOP_ADDR
#define CONN_INFRA_CFG_RC_CTL_1_TOP_XO_VCORE_OFF_STABLE_TIME_3_MASK 0xFF000000
#define CONN_INFRA_CFG_RC_CTL_1_TOP_XO_VCORE_OFF_STABLE_TIME_3_SHFT 24
#define CONN_INFRA_CFG_RC_CTL_1_TOP_XO_BG_STABLE_TIME_3_ADDR   CONN_INFRA_CFG_RC_CTL_1_TOP_ADDR
#define CONN_INFRA_CFG_RC_CTL_1_TOP_XO_BG_STABLE_TIME_3_MASK   0x00FF0000
#define CONN_INFRA_CFG_RC_CTL_1_TOP_XO_BG_STABLE_TIME_3_SHFT   16
#define CONN_INFRA_CFG_RC_CTL_1_TOP_XO_INI_STABLE_TIME_3_ADDR  CONN_INFRA_CFG_RC_CTL_1_TOP_ADDR
#define CONN_INFRA_CFG_RC_CTL_1_TOP_XO_INI_STABLE_TIME_3_MASK  0x0000FF00
#define CONN_INFRA_CFG_RC_CTL_1_TOP_XO_INI_STABLE_TIME_3_SHFT  8
#define CONN_INFRA_CFG_RC_CTL_1_TOP_XO_VCORE_RDY_STABLE_TIME_3_ADDR CONN_INFRA_CFG_RC_CTL_1_TOP_ADDR
#define CONN_INFRA_CFG_RC_CTL_1_TOP_XO_VCORE_RDY_STABLE_TIME_3_MASK 0x000000FF
#define CONN_INFRA_CFG_RC_CTL_1_TOP_XO_VCORE_RDY_STABLE_TIME_3_SHFT 0

#define CONN_INFRA_CFG_CONN2AP_MAILBOX_CONN2AP_MAILBOX_ADDR    CONN_INFRA_CFG_CONN2AP_MAILBOX_ADDR
#define CONN_INFRA_CFG_CONN2AP_MAILBOX_CONN2AP_MAILBOX_MASK    0xFFFFFFFF
#define CONN_INFRA_CFG_CONN2AP_MAILBOX_CONN2AP_MAILBOX_SHFT    0

#define CONN_INFRA_CFG_AP2CONN_MAILBOX_AP2CONN_MAILBOX_ADDR    CONN_INFRA_CFG_AP2CONN_MAILBOX_ADDR
#define CONN_INFRA_CFG_AP2CONN_MAILBOX_AP2CONN_MAILBOX_MASK    0xFFFFFFFF
#define CONN_INFRA_CFG_AP2CONN_MAILBOX_AP2CONN_MAILBOX_SHFT    0

#define CONN_INFRA_CFG_PWRCTRL0_CONN_INFRA_CFG_PWRCTRL0_RSV_1_ADDR CONN_INFRA_CFG_PWRCTRL0_ADDR
#define CONN_INFRA_CFG_PWRCTRL0_CONN_INFRA_CFG_PWRCTRL0_RSV_1_MASK 0xFFF00000
#define CONN_INFRA_CFG_PWRCTRL0_CONN_INFRA_CFG_PWRCTRL0_RSV_1_SHFT 20
#define CONN_INFRA_CFG_PWRCTRL0_CONN_INFRA_CFG_SLP_RDY_DIS_MASK_ADDR CONN_INFRA_CFG_PWRCTRL0_ADDR
#define CONN_INFRA_CFG_PWRCTRL0_CONN_INFRA_CFG_SLP_RDY_DIS_MASK_MASK 0x000F0000
#define CONN_INFRA_CFG_PWRCTRL0_CONN_INFRA_CFG_SLP_RDY_DIS_MASK_SHFT 16
#define CONN_INFRA_CFG_PWRCTRL0_CONN_INFRA_CFG_SLP_RDY_MASK_ADDR CONN_INFRA_CFG_PWRCTRL0_ADDR
#define CONN_INFRA_CFG_PWRCTRL0_CONN_INFRA_CFG_SLP_RDY_MASK_MASK 0x0000F000
#define CONN_INFRA_CFG_PWRCTRL0_CONN_INFRA_CFG_SLP_RDY_MASK_SHFT 12
#define CONN_INFRA_CFG_PWRCTRL0_CONN_INFRA_CFG_PWRCTRL0_RSV_0_ADDR CONN_INFRA_CFG_PWRCTRL0_ADDR
#define CONN_INFRA_CFG_PWRCTRL0_CONN_INFRA_CFG_PWRCTRL0_RSV_0_MASK 0x00000C00
#define CONN_INFRA_CFG_PWRCTRL0_CONN_INFRA_CFG_PWRCTRL0_RSV_0_SHFT 10
#define CONN_INFRA_CFG_PWRCTRL0_HWCTL_OSC_ON_CHECK_TOP_PWR_EN_ADDR CONN_INFRA_CFG_PWRCTRL0_ADDR
#define CONN_INFRA_CFG_PWRCTRL0_HWCTL_OSC_ON_CHECK_TOP_PWR_EN_MASK 0x00000200
#define CONN_INFRA_CFG_PWRCTRL0_HWCTL_OSC_ON_CHECK_TOP_PWR_EN_SHFT 9
#define CONN_INFRA_CFG_PWRCTRL0_CONN_INFRA_PWR_STAT_ADDR       CONN_INFRA_CFG_PWRCTRL0_ADDR
#define CONN_INFRA_CFG_PWRCTRL0_CONN_INFRA_PWR_STAT_MASK       0x000001F0
#define CONN_INFRA_CFG_PWRCTRL0_CONN_INFRA_PWR_STAT_SHFT       4
#define CONN_INFRA_CFG_PWRCTRL0_HW_CONTROL_ADDR                CONN_INFRA_CFG_PWRCTRL0_ADDR
#define CONN_INFRA_CFG_PWRCTRL0_HW_CONTROL_MASK                0x00000001
#define CONN_INFRA_CFG_PWRCTRL0_HW_CONTROL_SHFT                0

#define CONN_INFRA_CFG_FM_PWRCTRL0_CONN_INFRA_CFG_FM_PWRCTRL0_RSV_ADDR CONN_INFRA_CFG_FM_PWRCTRL0_ADDR
#define CONN_INFRA_CFG_FM_PWRCTRL0_CONN_INFRA_CFG_FM_PWRCTRL0_RSV_MASK 0xFFFFFF00
#define CONN_INFRA_CFG_FM_PWRCTRL0_CONN_INFRA_CFG_FM_PWRCTRL0_RSV_SHFT 8
#define CONN_INFRA_CFG_FM_PWRCTRL0_FMSYS_OSC_EN_ADDR           CONN_INFRA_CFG_FM_PWRCTRL0_ADDR
#define CONN_INFRA_CFG_FM_PWRCTRL0_FMSYS_OSC_EN_MASK           0x00000001
#define CONN_INFRA_CFG_FM_PWRCTRL0_FMSYS_OSC_EN_SHFT           0

#define CONN_INFRA_CFG_BT_PWRCTRL0_CONN_INFRA_CFG_BT_PWRCTRL0_RSV_ADDR CONN_INFRA_CFG_BT_PWRCTRL0_ADDR
#define CONN_INFRA_CFG_BT_PWRCTRL0_CONN_INFRA_CFG_BT_PWRCTRL0_RSV_MASK 0xFFFFFF00
#define CONN_INFRA_CFG_BT_PWRCTRL0_CONN_INFRA_CFG_BT_PWRCTRL0_RSV_SHFT 8
#define CONN_INFRA_CFG_BT_PWRCTRL0_BT_FUNCTION_EN_ADDR         CONN_INFRA_CFG_BT_PWRCTRL0_ADDR
#define CONN_INFRA_CFG_BT_PWRCTRL0_BT_FUNCTION_EN_MASK         0x00000001
#define CONN_INFRA_CFG_BT_PWRCTRL0_BT_FUNCTION_EN_SHFT         0

#define CONN_INFRA_CFG_GPS_PWRCTRL0_CONN_INFRA_CFG_GPS_PWRCTRL0_RSV_ADDR CONN_INFRA_CFG_GPS_PWRCTRL0_ADDR
#define CONN_INFRA_CFG_GPS_PWRCTRL0_CONN_INFRA_CFG_GPS_PWRCTRL0_RSV_MASK 0xFFFFFF00
#define CONN_INFRA_CFG_GPS_PWRCTRL0_CONN_INFRA_CFG_GPS_PWRCTRL0_RSV_SHFT 8
#define CONN_INFRA_CFG_GPS_PWRCTRL0_GP_FUNCTION_EN_ADDR        CONN_INFRA_CFG_GPS_PWRCTRL0_ADDR
#define CONN_INFRA_CFG_GPS_PWRCTRL0_GP_FUNCTION_EN_MASK        0x00000001
#define CONN_INFRA_CFG_GPS_PWRCTRL0_GP_FUNCTION_EN_SHFT        0

#define CONN_INFRA_CFG_BT_MANUAL_CTRL_BT_MANUAL_CTRL_ADDR      CONN_INFRA_CFG_BT_MANUAL_CTRL_ADDR
#define CONN_INFRA_CFG_BT_MANUAL_CTRL_BT_MANUAL_CTRL_MASK      0xFFFFFFFF
#define CONN_INFRA_CFG_BT_MANUAL_CTRL_BT_MANUAL_CTRL_SHFT      0

#define CONN_INFRA_CFG_GPS_MANUAL_CTRL_SW_GPS_OSC_RDY_ADDR     CONN_INFRA_CFG_GPS_MANUAL_CTRL_ADDR
#define CONN_INFRA_CFG_GPS_MANUAL_CTRL_SW_GPS_OSC_RDY_MASK     0x80000000
#define CONN_INFRA_CFG_GPS_MANUAL_CTRL_SW_GPS_OSC_RDY_SHFT     31
#define CONN_INFRA_CFG_GPS_MANUAL_CTRL_SW_GPS_OSC_ON_ADDR      CONN_INFRA_CFG_GPS_MANUAL_CTRL_ADDR
#define CONN_INFRA_CFG_GPS_MANUAL_CTRL_SW_GPS_OSC_ON_MASK      0x40000000
#define CONN_INFRA_CFG_GPS_MANUAL_CTRL_SW_GPS_OSC_ON_SHFT      30
#define CONN_INFRA_CFG_GPS_MANUAL_CTRL_SW_GPS_L1_SLP_CTL_ADDR  CONN_INFRA_CFG_GPS_MANUAL_CTRL_ADDR
#define CONN_INFRA_CFG_GPS_MANUAL_CTRL_SW_GPS_L1_SLP_CTL_MASK  0x20000000
#define CONN_INFRA_CFG_GPS_MANUAL_CTRL_SW_GPS_L1_SLP_CTL_SHFT  29
#define CONN_INFRA_CFG_GPS_MANUAL_CTRL_SW_GPS_L5_SLP_CTL_ADDR  CONN_INFRA_CFG_GPS_MANUAL_CTRL_ADDR
#define CONN_INFRA_CFG_GPS_MANUAL_CTRL_SW_GPS_L5_SLP_CTL_MASK  0x10000000
#define CONN_INFRA_CFG_GPS_MANUAL_CTRL_SW_GPS_L5_SLP_CTL_SHFT  28
#define CONN_INFRA_CFG_GPS_MANUAL_CTRL_SW_GPS_OSC_STL_ADDR     CONN_INFRA_CFG_GPS_MANUAL_CTRL_ADDR
#define CONN_INFRA_CFG_GPS_MANUAL_CTRL_SW_GPS_OSC_STL_MASK     0x08000000
#define CONN_INFRA_CFG_GPS_MANUAL_CTRL_SW_GPS_OSC_STL_SHFT     27
#define CONN_INFRA_CFG_GPS_MANUAL_CTRL_SW_GPS_TOP_OFF_PWR_CTL_ADDR CONN_INFRA_CFG_GPS_MANUAL_CTRL_ADDR
#define CONN_INFRA_CFG_GPS_MANUAL_CTRL_SW_GPS_TOP_OFF_PWR_CTL_MASK 0x04000000
#define CONN_INFRA_CFG_GPS_MANUAL_CTRL_SW_GPS_TOP_OFF_PWR_CTL_SHFT 26
#define CONN_INFRA_CFG_GPS_MANUAL_CTRL_SW_GPS_OSC_EN_ALL_ADDR  CONN_INFRA_CFG_GPS_MANUAL_CTRL_ADDR
#define CONN_INFRA_CFG_GPS_MANUAL_CTRL_SW_GPS_OSC_EN_ALL_MASK  0x02000000
#define CONN_INFRA_CFG_GPS_MANUAL_CTRL_SW_GPS_OSC_EN_ALL_SHFT  25
#define CONN_INFRA_CFG_GPS_MANUAL_CTRL_SW_GPS_HW_CONTROL_CLR_ADDR CONN_INFRA_CFG_GPS_MANUAL_CTRL_ADDR
#define CONN_INFRA_CFG_GPS_MANUAL_CTRL_SW_GPS_HW_CONTROL_CLR_MASK 0x01000000
#define CONN_INFRA_CFG_GPS_MANUAL_CTRL_SW_GPS_HW_CONTROL_CLR_SHFT 24
#define CONN_INFRA_CFG_GPS_MANUAL_CTRL_FORCE_GPS_BUS_CLK_EN_ADDR CONN_INFRA_CFG_GPS_MANUAL_CTRL_ADDR
#define CONN_INFRA_CFG_GPS_MANUAL_CTRL_FORCE_GPS_BUS_CLK_EN_MASK 0x00800000
#define CONN_INFRA_CFG_GPS_MANUAL_CTRL_FORCE_GPS_BUS_CLK_EN_SHFT 23
#define CONN_INFRA_CFG_GPS_MANUAL_CTRL_GPS_MANUAL_CTRL_ADDR    CONN_INFRA_CFG_GPS_MANUAL_CTRL_ADDR
#define CONN_INFRA_CFG_GPS_MANUAL_CTRL_GPS_MANUAL_CTRL_MASK    0x007FFFFF
#define CONN_INFRA_CFG_GPS_MANUAL_CTRL_GPS_MANUAL_CTRL_SHFT    0

#define CONN_INFRA_CFG_ADIE_CTL_ADIE_TOP_CKEN_ADDR             CONN_INFRA_CFG_ADIE_CTL_ADDR
#define CONN_INFRA_CFG_ADIE_CTL_ADIE_TOP_CKEN_MASK             0x00000002
#define CONN_INFRA_CFG_ADIE_CTL_ADIE_TOP_CKEN_SHFT             1
#define CONN_INFRA_CFG_ADIE_CTL_ADIE_RSTB_ADDR                 CONN_INFRA_CFG_ADIE_CTL_ADDR
#define CONN_INFRA_CFG_ADIE_CTL_ADIE_RSTB_MASK                 0x00000001
#define CONN_INFRA_CFG_ADIE_CTL_ADIE_RSTB_SHFT                 0

#define CONN_INFRA_CFG_CKGEN_BUS_ECO_FORCE_166_CR_EN_ADDR      CONN_INFRA_CFG_CKGEN_BUS_ADDR
#define CONN_INFRA_CFG_CKGEN_BUS_ECO_FORCE_166_CR_EN_MASK      0x20000000
#define CONN_INFRA_CFG_CKGEN_BUS_ECO_FORCE_166_CR_EN_SHFT      29
#define CONN_INFRA_CFG_CKGEN_BUS_RFSPI_DIV_EN_ADDR             CONN_INFRA_CFG_CKGEN_BUS_ADDR
#define CONN_INFRA_CFG_CKGEN_BUS_RFSPI_DIV_EN_MASK             0x10000000
#define CONN_INFRA_CFG_CKGEN_BUS_RFSPI_DIV_EN_SHFT             28
#define CONN_INFRA_CFG_CKGEN_BUS_CONN_BSI_CNS_HCLK_CKEN_ADDR   CONN_INFRA_CFG_CKGEN_BUS_ADDR
#define CONN_INFRA_CFG_CKGEN_BUS_CONN_BSI_CNS_HCLK_CKEN_MASK   0x08000000
#define CONN_INFRA_CFG_CKGEN_BUS_CONN_BSI_CNS_HCLK_CKEN_SHFT   27
#define CONN_INFRA_CFG_CKGEN_BUS_BSI_CNS_WPLL_CKEN_ADDR        CONN_INFRA_CFG_CKGEN_BUS_ADDR
#define CONN_INFRA_CFG_CKGEN_BUS_BSI_CNS_WPLL_CKEN_MASK        0x04000000
#define CONN_INFRA_CFG_CKGEN_BUS_BSI_CNS_WPLL_CKEN_SHFT        26
#define CONN_INFRA_CFG_CKGEN_BUS_BSI_CNS_HCLK_CKEN_ADDR        CONN_INFRA_CFG_CKGEN_BUS_ADDR
#define CONN_INFRA_CFG_CKGEN_BUS_BSI_CNS_HCLK_CKEN_MASK        0x02000000
#define CONN_INFRA_CFG_CKGEN_BUS_BSI_CNS_HCLK_CKEN_SHFT        25
#define CONN_INFRA_CFG_CKGEN_BUS_BSI_CNS_SRC_CKSEL_ADDR        CONN_INFRA_CFG_CKGEN_BUS_ADDR
#define CONN_INFRA_CFG_CKGEN_BUS_BSI_CNS_SRC_CKSEL_MASK        0x01000000
#define CONN_INFRA_CFG_CKGEN_BUS_BSI_CNS_SRC_CKSEL_SHFT        24
#define CONN_INFRA_CFG_CKGEN_BUS_HCLK_CKSEL_SWCTL_ADDR         CONN_INFRA_CFG_CKGEN_BUS_ADDR
#define CONN_INFRA_CFG_CKGEN_BUS_HCLK_CKSEL_SWCTL_MASK         0x00800000
#define CONN_INFRA_CFG_CKGEN_BUS_HCLK_CKSEL_SWCTL_SHFT         23
#define CONN_INFRA_CFG_CKGEN_BUS_HCLK_CKSEL_ADDR               CONN_INFRA_CFG_CKGEN_BUS_ADDR
#define CONN_INFRA_CFG_CKGEN_BUS_HCLK_CKSEL_MASK               0x00700000
#define CONN_INFRA_CFG_CKGEN_BUS_HCLK_CKSEL_SHFT               20
#define CONN_INFRA_CFG_CKGEN_BUS_FORCE_HCLK_CKSEL_VLD_ADDR     CONN_INFRA_CFG_CKGEN_BUS_ADDR
#define CONN_INFRA_CFG_CKGEN_BUS_FORCE_HCLK_CKSEL_VLD_MASK     0x00000040
#define CONN_INFRA_CFG_CKGEN_BUS_FORCE_HCLK_CKSEL_VLD_SHFT     6
#define CONN_INFRA_CFG_CKGEN_BUS_CONN_CO_EXT_UART_PTA_OSC_CKEN_ADDR CONN_INFRA_CFG_CKGEN_BUS_ADDR
#define CONN_INFRA_CFG_CKGEN_BUS_CONN_CO_EXT_UART_PTA_OSC_CKEN_MASK 0x00000020
#define CONN_INFRA_CFG_CKGEN_BUS_CONN_CO_EXT_UART_PTA_OSC_CKEN_SHFT 5
#define CONN_INFRA_CFG_CKGEN_BUS_CONN_CO_EXT_UART_PTA_HCLK_CKEN_ADDR CONN_INFRA_CFG_CKGEN_BUS_ADDR
#define CONN_INFRA_CFG_CKGEN_BUS_CONN_CO_EXT_UART_PTA_HCLK_CKEN_MASK 0x00000010
#define CONN_INFRA_CFG_CKGEN_BUS_CONN_CO_EXT_UART_PTA_HCLK_CKEN_SHFT 4
#define CONN_INFRA_CFG_CKGEN_BUS_CONN_CO_EXT_UART_PTA5_OSC_CKEN_ADDR CONN_INFRA_CFG_CKGEN_BUS_ADDR
#define CONN_INFRA_CFG_CKGEN_BUS_CONN_CO_EXT_UART_PTA5_OSC_CKEN_MASK 0x00000008
#define CONN_INFRA_CFG_CKGEN_BUS_CONN_CO_EXT_UART_PTA5_OSC_CKEN_SHFT 3
#define CONN_INFRA_CFG_CKGEN_BUS_CONN_CO_EXT_UART_PTA5_HCLK_CKEN_ADDR CONN_INFRA_CFG_CKGEN_BUS_ADDR
#define CONN_INFRA_CFG_CKGEN_BUS_CONN_CO_EXT_UART_PTA5_HCLK_CKEN_MASK 0x00000004
#define CONN_INFRA_CFG_CKGEN_BUS_CONN_CO_EXT_UART_PTA5_HCLK_CKEN_SHFT 2
#define CONN_INFRA_CFG_CKGEN_BUS_CONN_CO_EXT_FDD_COEX_HCLKCKEN_ADDR CONN_INFRA_CFG_CKGEN_BUS_ADDR
#define CONN_INFRA_CFG_CKGEN_BUS_CONN_CO_EXT_FDD_COEX_HCLKCKEN_MASK 0x00000002
#define CONN_INFRA_CFG_CKGEN_BUS_CONN_CO_EXT_FDD_COEX_HCLKCKEN_SHFT 1
#define CONN_INFRA_CFG_CKGEN_BUS_CONN_ANT_PINMUX_OSC_CKEN_ADDR CONN_INFRA_CFG_CKGEN_BUS_ADDR
#define CONN_INFRA_CFG_CKGEN_BUS_CONN_ANT_PINMUX_OSC_CKEN_MASK 0x00000001
#define CONN_INFRA_CFG_CKGEN_BUS_CONN_ANT_PINMUX_OSC_CKEN_SHFT 0

#define CONN_INFRA_CFG_DBG_MUX_SEL_CONN_INFRA_DBG_SELECTION_ADDR CONN_INFRA_CFG_DBG_MUX_SEL_ADDR
#define CONN_INFRA_CFG_DBG_MUX_SEL_CONN_INFRA_DBG_SELECTION_MASK 0x00000001
#define CONN_INFRA_CFG_DBG_MUX_SEL_CONN_INFRA_DBG_SELECTION_SHFT 0

#define CONN_INFRA_CFG_EMI_CTL_0_EMI_CTL_RSV_ADDR              CONN_INFRA_CFG_EMI_CTL_0_ADDR
#define CONN_INFRA_CFG_EMI_CTL_0_EMI_CTL_RSV_MASK              0xFFF00000
#define CONN_INFRA_CFG_EMI_CTL_0_EMI_CTL_RSV_SHFT              20
#define CONN_INFRA_CFG_EMI_CTL_0_EMI_SLPPROT_BP_APSRC_REQ_ADDR CONN_INFRA_CFG_EMI_CTL_0_ADDR
#define CONN_INFRA_CFG_EMI_CTL_0_EMI_SLPPROT_BP_APSRC_REQ_MASK 0x00080000
#define CONN_INFRA_CFG_EMI_CTL_0_EMI_SLPPROT_BP_APSRC_REQ_SHFT 19
#define CONN_INFRA_CFG_EMI_CTL_0_EMI_SLPPROT_BP_DDR_EN_ADDR    CONN_INFRA_CFG_EMI_CTL_0_ADDR
#define CONN_INFRA_CFG_EMI_CTL_0_EMI_SLPPROT_BP_DDR_EN_MASK    0x00040000
#define CONN_INFRA_CFG_EMI_CTL_0_EMI_SLPPROT_BP_DDR_EN_SHFT    18
#define CONN_INFRA_CFG_EMI_CTL_0_DDR_EN_BP_PROT_ADDR           CONN_INFRA_CFG_EMI_CTL_0_ADDR
#define CONN_INFRA_CFG_EMI_CTL_0_DDR_EN_BP_PROT_MASK           0x00020000
#define CONN_INFRA_CFG_EMI_CTL_0_DDR_EN_BP_PROT_SHFT           17
#define CONN_INFRA_CFG_EMI_CTL_0_CONN_EMI_BT_ONLY_RC_EN_ADDR   CONN_INFRA_CFG_EMI_CTL_0_ADDR
#define CONN_INFRA_CFG_EMI_CTL_0_CONN_EMI_BT_ONLY_RC_EN_MASK   0x00010000
#define CONN_INFRA_CFG_EMI_CTL_0_CONN_EMI_BT_ONLY_RC_EN_SHFT   16
#define CONN_INFRA_CFG_EMI_CTL_0_DDR_CNT_LIMIT_ADDR            CONN_INFRA_CFG_EMI_CTL_0_ADDR
#define CONN_INFRA_CFG_EMI_CTL_0_DDR_CNT_LIMIT_MASK            0x00007FF0
#define CONN_INFRA_CFG_EMI_CTL_0_DDR_CNT_LIMIT_SHFT            4
#define CONN_INFRA_CFG_EMI_CTL_0_CONN2AP_EMI_REQ_ADDR          CONN_INFRA_CFG_EMI_CTL_0_ADDR
#define CONN_INFRA_CFG_EMI_CTL_0_CONN2AP_EMI_REQ_MASK          0x00000004
#define CONN_INFRA_CFG_EMI_CTL_0_CONN2AP_EMI_REQ_SHFT          2
#define CONN_INFRA_CFG_EMI_CTL_0_EMI_CONN2AP_BUS_SLPPROT_BYPASS_ADDR CONN_INFRA_CFG_EMI_CTL_0_ADDR
#define CONN_INFRA_CFG_EMI_CTL_0_EMI_CONN2AP_BUS_SLPPROT_BYPASS_MASK 0x00000002
#define CONN_INFRA_CFG_EMI_CTL_0_EMI_CONN2AP_BUS_SLPPROT_BYPASS_SHFT 1
#define CONN_INFRA_CFG_EMI_CTL_0_CONN_EMI_RC_EN_ADDR           CONN_INFRA_CFG_EMI_CTL_0_ADDR
#define CONN_INFRA_CFG_EMI_CTL_0_CONN_EMI_RC_EN_MASK           0x00000001
#define CONN_INFRA_CFG_EMI_CTL_0_CONN_EMI_RC_EN_SHFT           0

#define CONN_INFRA_CFG_EMI_CTL_1_DDR_PROT_LIMIT_ADDR           CONN_INFRA_CFG_EMI_CTL_1_ADDR
#define CONN_INFRA_CFG_EMI_CTL_1_DDR_PROT_LIMIT_MASK           0xF0000000
#define CONN_INFRA_CFG_EMI_CTL_1_DDR_PROT_LIMIT_SHFT           28
#define CONN_INFRA_CFG_EMI_CTL_1_DDR_EN_ACK_ERR_ADDR           CONN_INFRA_CFG_EMI_CTL_1_ADDR
#define CONN_INFRA_CFG_EMI_CTL_1_DDR_EN_ACK_ERR_MASK           0x08000000
#define CONN_INFRA_CFG_EMI_CTL_1_DDR_EN_ACK_ERR_SHFT           27
#define CONN_INFRA_CFG_EMI_CTL_1_DDR_EN_ACK_ADDR               CONN_INFRA_CFG_EMI_CTL_1_ADDR
#define CONN_INFRA_CFG_EMI_CTL_1_DDR_EN_ACK_MASK               0x04000000
#define CONN_INFRA_CFG_EMI_CTL_1_DDR_EN_ACK_SHFT               26
#define CONN_INFRA_CFG_EMI_CTL_1_DDR_EN_ACK_BYPASS_ADDR        CONN_INFRA_CFG_EMI_CTL_1_ADDR
#define CONN_INFRA_CFG_EMI_CTL_1_DDR_EN_ACK_BYPASS_MASK        0x02000000
#define CONN_INFRA_CFG_EMI_CTL_1_DDR_EN_ACK_BYPASS_SHFT        25
#define CONN_INFRA_CFG_EMI_CTL_1_DDR_PROT_EN_ADDR              CONN_INFRA_CFG_EMI_CTL_1_ADDR
#define CONN_INFRA_CFG_EMI_CTL_1_DDR_PROT_EN_MASK              0x01000000
#define CONN_INFRA_CFG_EMI_CTL_1_DDR_PROT_EN_SHFT              24
#define CONN_INFRA_CFG_EMI_CTL_1_APSRC_PROT_LIMIT_ADDR         CONN_INFRA_CFG_EMI_CTL_1_ADDR
#define CONN_INFRA_CFG_EMI_CTL_1_APSRC_PROT_LIMIT_MASK         0x00F00000
#define CONN_INFRA_CFG_EMI_CTL_1_APSRC_PROT_LIMIT_SHFT         20
#define CONN_INFRA_CFG_EMI_CTL_1_APSRC_ACK_ERR_ADDR            CONN_INFRA_CFG_EMI_CTL_1_ADDR
#define CONN_INFRA_CFG_EMI_CTL_1_APSRC_ACK_ERR_MASK            0x00080000
#define CONN_INFRA_CFG_EMI_CTL_1_APSRC_ACK_ERR_SHFT            19
#define CONN_INFRA_CFG_EMI_CTL_1_APSRC_ACK_ADDR                CONN_INFRA_CFG_EMI_CTL_1_ADDR
#define CONN_INFRA_CFG_EMI_CTL_1_APSRC_ACK_MASK                0x00040000
#define CONN_INFRA_CFG_EMI_CTL_1_APSRC_ACK_SHFT                18
#define CONN_INFRA_CFG_EMI_CTL_1_APSRC_ACK_BYPASS_ADDR         CONN_INFRA_CFG_EMI_CTL_1_ADDR
#define CONN_INFRA_CFG_EMI_CTL_1_APSRC_ACK_BYPASS_MASK         0x00020000
#define CONN_INFRA_CFG_EMI_CTL_1_APSRC_ACK_BYPASS_SHFT         17
#define CONN_INFRA_CFG_EMI_CTL_1_APSRC_PROT_EN_ADDR            CONN_INFRA_CFG_EMI_CTL_1_ADDR
#define CONN_INFRA_CFG_EMI_CTL_1_APSRC_PROT_EN_MASK            0x00010000
#define CONN_INFRA_CFG_EMI_CTL_1_APSRC_PROT_EN_SHFT            16
#define CONN_INFRA_CFG_EMI_CTL_1_AP_BUS_PROT_LIMIT_ADDR        CONN_INFRA_CFG_EMI_CTL_1_ADDR
#define CONN_INFRA_CFG_EMI_CTL_1_AP_BUS_PROT_LIMIT_MASK        0x0000F000
#define CONN_INFRA_CFG_EMI_CTL_1_AP_BUS_PROT_LIMIT_SHFT        12
#define CONN_INFRA_CFG_EMI_CTL_1_AP_BUS_ACK_ERR_ADDR           CONN_INFRA_CFG_EMI_CTL_1_ADDR
#define CONN_INFRA_CFG_EMI_CTL_1_AP_BUS_ACK_ERR_MASK           0x00000800
#define CONN_INFRA_CFG_EMI_CTL_1_AP_BUS_ACK_ERR_SHFT           11
#define CONN_INFRA_CFG_EMI_CTL_1_AP_BUS_ACK_ADDR               CONN_INFRA_CFG_EMI_CTL_1_ADDR
#define CONN_INFRA_CFG_EMI_CTL_1_AP_BUS_ACK_MASK               0x00000400
#define CONN_INFRA_CFG_EMI_CTL_1_AP_BUS_ACK_SHFT               10
#define CONN_INFRA_CFG_EMI_CTL_1_AP_BUS_ACK_BYPASS_ADDR        CONN_INFRA_CFG_EMI_CTL_1_ADDR
#define CONN_INFRA_CFG_EMI_CTL_1_AP_BUS_ACK_BYPASS_MASK        0x00000200
#define CONN_INFRA_CFG_EMI_CTL_1_AP_BUS_ACK_BYPASS_SHFT        9
#define CONN_INFRA_CFG_EMI_CTL_1_AP_BUS_PROT_EN_ADDR           CONN_INFRA_CFG_EMI_CTL_1_ADDR
#define CONN_INFRA_CFG_EMI_CTL_1_AP_BUS_PROT_EN_MASK           0x00000100
#define CONN_INFRA_CFG_EMI_CTL_1_AP_BUS_PROT_EN_SHFT           8
#define CONN_INFRA_CFG_EMI_CTL_1_SRCCLKENA_PROT_LIMIT_ADDR     CONN_INFRA_CFG_EMI_CTL_1_ADDR
#define CONN_INFRA_CFG_EMI_CTL_1_SRCCLKENA_PROT_LIMIT_MASK     0x000000F0
#define CONN_INFRA_CFG_EMI_CTL_1_SRCCLKENA_PROT_LIMIT_SHFT     4
#define CONN_INFRA_CFG_EMI_CTL_1_SRCCLKENA_ACK_ERR_ADDR        CONN_INFRA_CFG_EMI_CTL_1_ADDR
#define CONN_INFRA_CFG_EMI_CTL_1_SRCCLKENA_ACK_ERR_MASK        0x00000008
#define CONN_INFRA_CFG_EMI_CTL_1_SRCCLKENA_ACK_ERR_SHFT        3
#define CONN_INFRA_CFG_EMI_CTL_1_SRCCLKENA_ACK_ADDR            CONN_INFRA_CFG_EMI_CTL_1_ADDR
#define CONN_INFRA_CFG_EMI_CTL_1_SRCCLKENA_ACK_MASK            0x00000004
#define CONN_INFRA_CFG_EMI_CTL_1_SRCCLKENA_ACK_SHFT            2
#define CONN_INFRA_CFG_EMI_CTL_1_SRCCLKENA_ACK_BYPASS_ADDR     CONN_INFRA_CFG_EMI_CTL_1_ADDR
#define CONN_INFRA_CFG_EMI_CTL_1_SRCCLKENA_ACK_BYPASS_MASK     0x00000002
#define CONN_INFRA_CFG_EMI_CTL_1_SRCCLKENA_ACK_BYPASS_SHFT     1
#define CONN_INFRA_CFG_EMI_CTL_1_SRCCLKENA_PROT_EN_ADDR        CONN_INFRA_CFG_EMI_CTL_1_ADDR
#define CONN_INFRA_CFG_EMI_CTL_1_SRCCLKENA_PROT_EN_MASK        0x00000001
#define CONN_INFRA_CFG_EMI_CTL_1_SRCCLKENA_PROT_EN_SHFT        0

#define CONN_INFRA_CFG_EMI_PROBE_HW_CONN_DDR_EN_DIS_ADDR       CONN_INFRA_CFG_EMI_PROBE_ADDR
#define CONN_INFRA_CFG_EMI_PROBE_HW_CONN_DDR_EN_DIS_MASK       0x80000000
#define CONN_INFRA_CFG_EMI_PROBE_HW_CONN_DDR_EN_DIS_SHFT       31
#define CONN_INFRA_CFG_EMI_PROBE_HW_CONN_APSRC_REQ_DIS_ADDR    CONN_INFRA_CFG_EMI_PROBE_ADDR
#define CONN_INFRA_CFG_EMI_PROBE_HW_CONN_APSRC_REQ_DIS_MASK    0x40000000
#define CONN_INFRA_CFG_EMI_PROBE_HW_CONN_APSRC_REQ_DIS_SHFT    30
#define CONN_INFRA_CFG_EMI_PROBE_HW_CONN_AP_BUS_REQ_DIS_ADDR   CONN_INFRA_CFG_EMI_PROBE_ADDR
#define CONN_INFRA_CFG_EMI_PROBE_HW_CONN_AP_BUS_REQ_DIS_MASK   0x20000000
#define CONN_INFRA_CFG_EMI_PROBE_HW_CONN_AP_BUS_REQ_DIS_SHFT   29
#define CONN_INFRA_CFG_EMI_PROBE_HW_CONN_SRCCLKENA_EMI_DIS_ADDR CONN_INFRA_CFG_EMI_PROBE_ADDR
#define CONN_INFRA_CFG_EMI_PROBE_HW_CONN_SRCCLKENA_EMI_DIS_MASK 0x10000000
#define CONN_INFRA_CFG_EMI_PROBE_HW_CONN_SRCCLKENA_EMI_DIS_SHFT 28
#define CONN_INFRA_CFG_EMI_PROBE_CONN_SRCCLKENA_PRE_ADDR       CONN_INFRA_CFG_EMI_PROBE_ADDR
#define CONN_INFRA_CFG_EMI_PROBE_CONN_SRCCLKENA_PRE_MASK       0x08000000
#define CONN_INFRA_CFG_EMI_PROBE_CONN_SRCCLKENA_PRE_SHFT       27
#define CONN_INFRA_CFG_EMI_PROBE_DDR_TIMEOUT_ADDR              CONN_INFRA_CFG_EMI_PROBE_ADDR
#define CONN_INFRA_CFG_EMI_PROBE_DDR_TIMEOUT_MASK              0x04000000
#define CONN_INFRA_CFG_EMI_PROBE_DDR_TIMEOUT_SHFT              26
#define CONN_INFRA_CFG_EMI_PROBE_EMI_REQ_DIS_ADDR              CONN_INFRA_CFG_EMI_PROBE_ADDR
#define CONN_INFRA_CFG_EMI_PROBE_EMI_REQ_DIS_MASK              0x02000000
#define CONN_INFRA_CFG_EMI_PROBE_EMI_REQ_DIS_SHFT              25
#define CONN_INFRA_CFG_EMI_PROBE_EMI_REQ_ALL_ADDR              CONN_INFRA_CFG_EMI_PROBE_ADDR
#define CONN_INFRA_CFG_EMI_PROBE_EMI_REQ_ALL_MASK              0x01000000
#define CONN_INFRA_CFG_EMI_PROBE_EMI_REQ_ALL_SHFT              24
#define CONN_INFRA_CFG_EMI_PROBE_DDR_EN_STABLE_ADDR            CONN_INFRA_CFG_EMI_PROBE_ADDR
#define CONN_INFRA_CFG_EMI_PROBE_DDR_EN_STABLE_MASK            0x00800000
#define CONN_INFRA_CFG_EMI_PROBE_DDR_EN_STABLE_SHFT            23
#define CONN_INFRA_CFG_EMI_PROBE_AP_BUS_STABLE_ADDR            CONN_INFRA_CFG_EMI_PROBE_ADDR
#define CONN_INFRA_CFG_EMI_PROBE_AP_BUS_STABLE_MASK            0x00400000
#define CONN_INFRA_CFG_EMI_PROBE_AP_BUS_STABLE_SHFT            22
#define CONN_INFRA_CFG_EMI_PROBE_APSRC_STABLE_ADDR             CONN_INFRA_CFG_EMI_PROBE_ADDR
#define CONN_INFRA_CFG_EMI_PROBE_APSRC_STABLE_MASK             0x00200000
#define CONN_INFRA_CFG_EMI_PROBE_APSRC_STABLE_SHFT             21
#define CONN_INFRA_CFG_EMI_PROBE_SRCCLKENA_STABLE_ADDR         CONN_INFRA_CFG_EMI_PROBE_ADDR
#define CONN_INFRA_CFG_EMI_PROBE_SRCCLKENA_STABLE_MASK         0x00100000
#define CONN_INFRA_CFG_EMI_PROBE_SRCCLKENA_STABLE_SHFT         20
#define CONN_INFRA_CFG_EMI_PROBE_DDR_EN_STABLE_REG_ADDR        CONN_INFRA_CFG_EMI_PROBE_ADDR
#define CONN_INFRA_CFG_EMI_PROBE_DDR_EN_STABLE_REG_MASK        0x00080000
#define CONN_INFRA_CFG_EMI_PROBE_DDR_EN_STABLE_REG_SHFT        19
#define CONN_INFRA_CFG_EMI_PROBE_AP_BUS_STABLE_REG_ADDR        CONN_INFRA_CFG_EMI_PROBE_ADDR
#define CONN_INFRA_CFG_EMI_PROBE_AP_BUS_STABLE_REG_MASK        0x00040000
#define CONN_INFRA_CFG_EMI_PROBE_AP_BUS_STABLE_REG_SHFT        18
#define CONN_INFRA_CFG_EMI_PROBE_APSRC_STABLE_REG_ADDR         CONN_INFRA_CFG_EMI_PROBE_ADDR
#define CONN_INFRA_CFG_EMI_PROBE_APSRC_STABLE_REG_MASK         0x00020000
#define CONN_INFRA_CFG_EMI_PROBE_APSRC_STABLE_REG_SHFT         17
#define CONN_INFRA_CFG_EMI_PROBE_SRCCLKENA_STABLE_REG_ADDR     CONN_INFRA_CFG_EMI_PROBE_ADDR
#define CONN_INFRA_CFG_EMI_PROBE_SRCCLKENA_STABLE_REG_MASK     0x00010000
#define CONN_INFRA_CFG_EMI_PROBE_SRCCLKENA_STABLE_REG_SHFT     16
#define CONN_INFRA_CFG_EMI_PROBE_CONN2AP_BUS_SLPPROT_EN_ADDR   CONN_INFRA_CFG_EMI_PROBE_ADDR
#define CONN_INFRA_CFG_EMI_PROBE_CONN2AP_BUS_SLPPROT_EN_MASK   0x00008000
#define CONN_INFRA_CFG_EMI_PROBE_CONN2AP_BUS_SLPPROT_EN_SHFT   15
#define CONN_INFRA_CFG_EMI_PROBE_CONN2AP_BUS_SLPPORT_RDY_ADDR  CONN_INFRA_CFG_EMI_PROBE_ADDR
#define CONN_INFRA_CFG_EMI_PROBE_CONN2AP_BUS_SLPPORT_RDY_MASK  0x00004000
#define CONN_INFRA_CFG_EMI_PROBE_CONN2AP_BUS_SLPPORT_RDY_SHFT  14
#define CONN_INFRA_CFG_EMI_PROBE_CONN2AP_EMI_REQ_ADDR          CONN_INFRA_CFG_EMI_PROBE_ADDR
#define CONN_INFRA_CFG_EMI_PROBE_CONN2AP_EMI_REQ_MASK          0x00002000
#define CONN_INFRA_CFG_EMI_PROBE_CONN2AP_EMI_REQ_SHFT          13
#define CONN_INFRA_CFG_EMI_PROBE_CONN2AP_BUS_IDLE_ADDR         CONN_INFRA_CFG_EMI_PROBE_ADDR
#define CONN_INFRA_CFG_EMI_PROBE_CONN2AP_BUS_IDLE_MASK         0x00001000
#define CONN_INFRA_CFG_EMI_PROBE_CONN2AP_BUS_IDLE_SHFT         12
#define CONN_INFRA_CFG_EMI_PROBE_DDR_EN_ACK_SYNC_ADDR          CONN_INFRA_CFG_EMI_PROBE_ADDR
#define CONN_INFRA_CFG_EMI_PROBE_DDR_EN_ACK_SYNC_MASK          0x00000800
#define CONN_INFRA_CFG_EMI_PROBE_DDR_EN_ACK_SYNC_SHFT          11
#define CONN_INFRA_CFG_EMI_PROBE_APSRC_ACK_SYNC_ADDR           CONN_INFRA_CFG_EMI_PROBE_ADDR
#define CONN_INFRA_CFG_EMI_PROBE_APSRC_ACK_SYNC_MASK           0x00000400
#define CONN_INFRA_CFG_EMI_PROBE_APSRC_ACK_SYNC_SHFT           10
#define CONN_INFRA_CFG_EMI_PROBE_AP_BUS_ACK_SYNC_ADDR          CONN_INFRA_CFG_EMI_PROBE_ADDR
#define CONN_INFRA_CFG_EMI_PROBE_AP_BUS_ACK_SYNC_MASK          0x00000200
#define CONN_INFRA_CFG_EMI_PROBE_AP_BUS_ACK_SYNC_SHFT          9
#define CONN_INFRA_CFG_EMI_PROBE_SRCCLKENA_ACK_SYNC_ADDR       CONN_INFRA_CFG_EMI_PROBE_ADDR
#define CONN_INFRA_CFG_EMI_PROBE_SRCCLKENA_ACK_SYNC_MASK       0x00000100
#define CONN_INFRA_CFG_EMI_PROBE_SRCCLKENA_ACK_SYNC_SHFT       8
#define CONN_INFRA_CFG_EMI_PROBE_CONN_DDR_EN_ACK_ADDR          CONN_INFRA_CFG_EMI_PROBE_ADDR
#define CONN_INFRA_CFG_EMI_PROBE_CONN_DDR_EN_ACK_MASK          0x00000080
#define CONN_INFRA_CFG_EMI_PROBE_CONN_DDR_EN_ACK_SHFT          7
#define CONN_INFRA_CFG_EMI_PROBE_CONN_APSRC_ACK_ADDR           CONN_INFRA_CFG_EMI_PROBE_ADDR
#define CONN_INFRA_CFG_EMI_PROBE_CONN_APSRC_ACK_MASK           0x00000040
#define CONN_INFRA_CFG_EMI_PROBE_CONN_APSRC_ACK_SHFT           6
#define CONN_INFRA_CFG_EMI_PROBE_CONN_AP_BUS_ACK_ADDR          CONN_INFRA_CFG_EMI_PROBE_ADDR
#define CONN_INFRA_CFG_EMI_PROBE_CONN_AP_BUS_ACK_MASK          0x00000020
#define CONN_INFRA_CFG_EMI_PROBE_CONN_AP_BUS_ACK_SHFT          5
#define CONN_INFRA_CFG_EMI_PROBE_CONN_SRCCCLKENA_ACK_ADDR      CONN_INFRA_CFG_EMI_PROBE_ADDR
#define CONN_INFRA_CFG_EMI_PROBE_CONN_SRCCCLKENA_ACK_MASK      0x00000010
#define CONN_INFRA_CFG_EMI_PROBE_CONN_SRCCCLKENA_ACK_SHFT      4
#define CONN_INFRA_CFG_EMI_PROBE_CONN_DDR_EN_ADDR              CONN_INFRA_CFG_EMI_PROBE_ADDR
#define CONN_INFRA_CFG_EMI_PROBE_CONN_DDR_EN_MASK              0x00000008
#define CONN_INFRA_CFG_EMI_PROBE_CONN_DDR_EN_SHFT              3
#define CONN_INFRA_CFG_EMI_PROBE_CONN_APSRC_ADDR               CONN_INFRA_CFG_EMI_PROBE_ADDR
#define CONN_INFRA_CFG_EMI_PROBE_CONN_APSRC_MASK               0x00000004
#define CONN_INFRA_CFG_EMI_PROBE_CONN_APSRC_SHFT               2
#define CONN_INFRA_CFG_EMI_PROBE_CONN_AP_BUS_ADDR              CONN_INFRA_CFG_EMI_PROBE_ADDR
#define CONN_INFRA_CFG_EMI_PROBE_CONN_AP_BUS_MASK              0x00000002
#define CONN_INFRA_CFG_EMI_PROBE_CONN_AP_BUS_SHFT              1
#define CONN_INFRA_CFG_EMI_PROBE_CONN_SRCCCLKENA_ADDR          CONN_INFRA_CFG_EMI_PROBE_ADDR
#define CONN_INFRA_CFG_EMI_PROBE_CONN_SRCCCLKENA_MASK          0x00000001
#define CONN_INFRA_CFG_EMI_PROBE_CONN_SRCCCLKENA_SHFT          0

#define CONN_INFRA_CFG_EMI_PROBE_1_EMI_PROBE_1_ADDR            CONN_INFRA_CFG_EMI_PROBE_1_ADDR
#define CONN_INFRA_CFG_EMI_PROBE_1_EMI_PROBE_1_MASK            0xFFFFFFFF
#define CONN_INFRA_CFG_EMI_PROBE_1_EMI_PROBE_1_SHFT            0

#define CONN_INFRA_CFG_EMI_CTL_TOP_EMI_CTL_RSV_TOP_ADDR        CONN_INFRA_CFG_EMI_CTL_TOP_ADDR
#define CONN_INFRA_CFG_EMI_CTL_TOP_EMI_CTL_RSV_TOP_MASK        0x0000FFE0
#define CONN_INFRA_CFG_EMI_CTL_TOP_EMI_CTL_RSV_TOP_SHFT        5
#define CONN_INFRA_CFG_EMI_CTL_TOP_SW_CONN_DDR_EN_TOP_ADDR     CONN_INFRA_CFG_EMI_CTL_TOP_ADDR
#define CONN_INFRA_CFG_EMI_CTL_TOP_SW_CONN_DDR_EN_TOP_MASK     0x00000010
#define CONN_INFRA_CFG_EMI_CTL_TOP_SW_CONN_DDR_EN_TOP_SHFT     4
#define CONN_INFRA_CFG_EMI_CTL_TOP_SW_CONN_APSRC_REQ_TOP_ADDR  CONN_INFRA_CFG_EMI_CTL_TOP_ADDR
#define CONN_INFRA_CFG_EMI_CTL_TOP_SW_CONN_APSRC_REQ_TOP_MASK  0x00000008
#define CONN_INFRA_CFG_EMI_CTL_TOP_SW_CONN_APSRC_REQ_TOP_SHFT  3
#define CONN_INFRA_CFG_EMI_CTL_TOP_SW_CONN_AP_BUS_REQ_TOP_ADDR CONN_INFRA_CFG_EMI_CTL_TOP_ADDR
#define CONN_INFRA_CFG_EMI_CTL_TOP_SW_CONN_AP_BUS_REQ_TOP_MASK 0x00000004
#define CONN_INFRA_CFG_EMI_CTL_TOP_SW_CONN_AP_BUS_REQ_TOP_SHFT 2
#define CONN_INFRA_CFG_EMI_CTL_TOP_SW_CONN_SRCCLKENA_TOP_ADDR  CONN_INFRA_CFG_EMI_CTL_TOP_ADDR
#define CONN_INFRA_CFG_EMI_CTL_TOP_SW_CONN_SRCCLKENA_TOP_MASK  0x00000002
#define CONN_INFRA_CFG_EMI_CTL_TOP_SW_CONN_SRCCLKENA_TOP_SHFT  1
#define CONN_INFRA_CFG_EMI_CTL_TOP_EMI_REQ_TOP_ADDR            CONN_INFRA_CFG_EMI_CTL_TOP_ADDR
#define CONN_INFRA_CFG_EMI_CTL_TOP_EMI_REQ_TOP_MASK            0x00000001
#define CONN_INFRA_CFG_EMI_CTL_TOP_EMI_REQ_TOP_SHFT            0

#define CONN_INFRA_CFG_EMI_CTL_WF_EMI_CTL_RSV_WF_ADDR          CONN_INFRA_CFG_EMI_CTL_WF_ADDR
#define CONN_INFRA_CFG_EMI_CTL_WF_EMI_CTL_RSV_WF_MASK          0x0000FFE0
#define CONN_INFRA_CFG_EMI_CTL_WF_EMI_CTL_RSV_WF_SHFT          5
#define CONN_INFRA_CFG_EMI_CTL_WF_SW_CONN_DDR_EN_WF_ADDR       CONN_INFRA_CFG_EMI_CTL_WF_ADDR
#define CONN_INFRA_CFG_EMI_CTL_WF_SW_CONN_DDR_EN_WF_MASK       0x00000010
#define CONN_INFRA_CFG_EMI_CTL_WF_SW_CONN_DDR_EN_WF_SHFT       4
#define CONN_INFRA_CFG_EMI_CTL_WF_SW_CONN_APSRC_REQ_WF_ADDR    CONN_INFRA_CFG_EMI_CTL_WF_ADDR
#define CONN_INFRA_CFG_EMI_CTL_WF_SW_CONN_APSRC_REQ_WF_MASK    0x00000008
#define CONN_INFRA_CFG_EMI_CTL_WF_SW_CONN_APSRC_REQ_WF_SHFT    3
#define CONN_INFRA_CFG_EMI_CTL_WF_SW_CONN_AP_BUS_REQ_WF_ADDR   CONN_INFRA_CFG_EMI_CTL_WF_ADDR
#define CONN_INFRA_CFG_EMI_CTL_WF_SW_CONN_AP_BUS_REQ_WF_MASK   0x00000004
#define CONN_INFRA_CFG_EMI_CTL_WF_SW_CONN_AP_BUS_REQ_WF_SHFT   2
#define CONN_INFRA_CFG_EMI_CTL_WF_SW_CONN_SRCCLKENA_WF_ADDR    CONN_INFRA_CFG_EMI_CTL_WF_ADDR
#define CONN_INFRA_CFG_EMI_CTL_WF_SW_CONN_SRCCLKENA_WF_MASK    0x00000002
#define CONN_INFRA_CFG_EMI_CTL_WF_SW_CONN_SRCCLKENA_WF_SHFT    1
#define CONN_INFRA_CFG_EMI_CTL_WF_EMI_REQ_WF_ADDR              CONN_INFRA_CFG_EMI_CTL_WF_ADDR
#define CONN_INFRA_CFG_EMI_CTL_WF_EMI_REQ_WF_MASK              0x00000001
#define CONN_INFRA_CFG_EMI_CTL_WF_EMI_REQ_WF_SHFT              0

#define CONN_INFRA_CFG_EMI_CTL_BT_EMI_CTL_RSV_BT_ADDR          CONN_INFRA_CFG_EMI_CTL_BT_ADDR
#define CONN_INFRA_CFG_EMI_CTL_BT_EMI_CTL_RSV_BT_MASK          0x0000FFE0
#define CONN_INFRA_CFG_EMI_CTL_BT_EMI_CTL_RSV_BT_SHFT          5
#define CONN_INFRA_CFG_EMI_CTL_BT_SW_CONN_DDR_EN_BT_ADDR       CONN_INFRA_CFG_EMI_CTL_BT_ADDR
#define CONN_INFRA_CFG_EMI_CTL_BT_SW_CONN_DDR_EN_BT_MASK       0x00000010
#define CONN_INFRA_CFG_EMI_CTL_BT_SW_CONN_DDR_EN_BT_SHFT       4
#define CONN_INFRA_CFG_EMI_CTL_BT_SW_CONN_APSRC_REQ_BT_ADDR    CONN_INFRA_CFG_EMI_CTL_BT_ADDR
#define CONN_INFRA_CFG_EMI_CTL_BT_SW_CONN_APSRC_REQ_BT_MASK    0x00000008
#define CONN_INFRA_CFG_EMI_CTL_BT_SW_CONN_APSRC_REQ_BT_SHFT    3
#define CONN_INFRA_CFG_EMI_CTL_BT_SW_CONN_AP_BUS_REQ_BT_ADDR   CONN_INFRA_CFG_EMI_CTL_BT_ADDR
#define CONN_INFRA_CFG_EMI_CTL_BT_SW_CONN_AP_BUS_REQ_BT_MASK   0x00000004
#define CONN_INFRA_CFG_EMI_CTL_BT_SW_CONN_AP_BUS_REQ_BT_SHFT   2
#define CONN_INFRA_CFG_EMI_CTL_BT_SW_CONN_SRCCLKENA_BT_ADDR    CONN_INFRA_CFG_EMI_CTL_BT_ADDR
#define CONN_INFRA_CFG_EMI_CTL_BT_SW_CONN_SRCCLKENA_BT_MASK    0x00000002
#define CONN_INFRA_CFG_EMI_CTL_BT_SW_CONN_SRCCLKENA_BT_SHFT    1
#define CONN_INFRA_CFG_EMI_CTL_BT_EMI_REQ_BT_ADDR              CONN_INFRA_CFG_EMI_CTL_BT_ADDR
#define CONN_INFRA_CFG_EMI_CTL_BT_EMI_REQ_BT_MASK              0x00000001
#define CONN_INFRA_CFG_EMI_CTL_BT_EMI_REQ_BT_SHFT              0

#define CONN_INFRA_CFG_EMI_CTL_GPS_EMI_CTL_RSV_GPS_ADDR        CONN_INFRA_CFG_EMI_CTL_GPS_ADDR
#define CONN_INFRA_CFG_EMI_CTL_GPS_EMI_CTL_RSV_GPS_MASK        0x0000FFE0
#define CONN_INFRA_CFG_EMI_CTL_GPS_EMI_CTL_RSV_GPS_SHFT        5
#define CONN_INFRA_CFG_EMI_CTL_GPS_SW_CONN_DDR_EN_GPS_ADDR     CONN_INFRA_CFG_EMI_CTL_GPS_ADDR
#define CONN_INFRA_CFG_EMI_CTL_GPS_SW_CONN_DDR_EN_GPS_MASK     0x00000010
#define CONN_INFRA_CFG_EMI_CTL_GPS_SW_CONN_DDR_EN_GPS_SHFT     4
#define CONN_INFRA_CFG_EMI_CTL_GPS_SW_CONN_APSRC_REQ_GPS_ADDR  CONN_INFRA_CFG_EMI_CTL_GPS_ADDR
#define CONN_INFRA_CFG_EMI_CTL_GPS_SW_CONN_APSRC_REQ_GPS_MASK  0x00000008
#define CONN_INFRA_CFG_EMI_CTL_GPS_SW_CONN_APSRC_REQ_GPS_SHFT  3
#define CONN_INFRA_CFG_EMI_CTL_GPS_SW_CONN_AP_BUS_REQ_GPS_ADDR CONN_INFRA_CFG_EMI_CTL_GPS_ADDR
#define CONN_INFRA_CFG_EMI_CTL_GPS_SW_CONN_AP_BUS_REQ_GPS_MASK 0x00000004
#define CONN_INFRA_CFG_EMI_CTL_GPS_SW_CONN_AP_BUS_REQ_GPS_SHFT 2
#define CONN_INFRA_CFG_EMI_CTL_GPS_SW_CONN_SRCCLKENA_GPS_ADDR  CONN_INFRA_CFG_EMI_CTL_GPS_ADDR
#define CONN_INFRA_CFG_EMI_CTL_GPS_SW_CONN_SRCCLKENA_GPS_MASK  0x00000002
#define CONN_INFRA_CFG_EMI_CTL_GPS_SW_CONN_SRCCLKENA_GPS_SHFT  1
#define CONN_INFRA_CFG_EMI_CTL_GPS_EMI_REQ_GPS_ADDR            CONN_INFRA_CFG_EMI_CTL_GPS_ADDR
#define CONN_INFRA_CFG_EMI_CTL_GPS_EMI_REQ_GPS_MASK            0x00000001
#define CONN_INFRA_CFG_EMI_CTL_GPS_EMI_REQ_GPS_SHFT            0

#endif /* __CONN_INFRA_CFG_REGS_H__ */

